Bapat; Sachin
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bapat; Sachin.The latest application filed is for "adaptive low power and high performance logic design and physical design techniques".
- Bapat; Sachin - Bangalore KRN IN
| Patent | Date |
|---|---|
| Flip-flop with reduced retention voltage Grant 9,673,786 - Rasouli , et al. June 6, 2 | 2017-06-06 |
| Adaptive Low Power And High Performance Logic Design And Physical Design Techniques App 20160217227 - PARKAR; Peeyush Kumar ; et al. | 2016-07-28 |
| Method and apparatus for clock power saving in multiport latch arrays Grant 9,053,773 - Marimuthu , et al. June 9, 2 | 2015-06-09 |
| Flip-flop With Reduced Retention Voltage App 20140306735 - Rasouli; Seid Hadi ; et al. | 2014-10-16 |
| Method And Apparatus For Clock Power Saving In Multiport Latch Arrays App 20140177344 - MARIMUTHU; Saravanan ; et al. | 2014-06-26 |
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