Bao; Xu Sheng Patent Filings

Patent	Date
Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB App 20200335358 - Lin; Yaojian ; et al.	2020-10-22
Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB Grant 10,741,416 - Lin , et al. A	2020-08-11
Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB App 20170263470 - Lin; Yaojian ; et al.	2017-09-14
Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB Grant 9,685,350 - Lin , et al. June 20, 2	2017-06-20
Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region Grant 9,620,557 - Chow , et al. April 11, 2	2017-04-11
Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region App 20160104731 - Chow; Seng Guan ; et al.	2016-04-14
Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB App 20140252573 - Lin; Yaojian ; et al.	2014-09-11
Semiconductor package with passivation island for reducing stress on solder bumps Grant 7,968,445 - Lin , et al. June 28, 2	2011-06-28
Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps App 20100105200 - Lin; Yaojian ; et al.	2010-04-29
Semiconductor package with passivation island for reducing stress on solder bumps Grant 7,667,335 - Lin , et al. February 23, 2	2010-02-23
Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps App 20090079070 - Lin; Yaojian ; et al.	2009-03-26

Patent

Date

Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
App 20200335358 - Lin; Yaojian ; et al.

2020-10-22

Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
Grant 10,741,416 - Lin , et al. A

2020-08-11

Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
App 20170263470 - Lin; Yaojian ; et al.

2017-09-14

Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
Grant 9,685,350 - Lin , et al. June 20, 2

2017-06-20

Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
Grant 9,620,557 - Chow , et al. April 11, 2

2017-04-11

Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
App 20160104731 - Chow; Seng Guan ; et al.

2016-04-14

Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
App 20140252573 - Lin; Yaojian ; et al.

2014-09-11

Semiconductor package with passivation island for reducing stress on solder bumps
Grant 7,968,445 - Lin , et al. June 28, 2

2011-06-28

Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps
App 20100105200 - Lin; Yaojian ; et al.

2010-04-29

Semiconductor package with passivation island for reducing stress on solder bumps
Grant 7,667,335 - Lin , et al. February 23, 2

2010-02-23

Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps
App 20090079070 - Lin; Yaojian ; et al.

2009-03-26

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Bao; Xu Sheng

Patent Applications and Registrations