BANG; David

Patent Applications and Registrations

Patent applications and USPTO patent grants for BANG; David.The latest application filed is for "one-mask mtj integration for stt mram".

Company Profile

0.14.7

BANG; David - San Diego CA
Bang; David - La Jolla CA
Bang; David - Palo Alto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
One-mask Mtj Integration For Stt Mram App 20160020383 - KANG; Seung H. ; et al.	2016-01-21
One-mask MTJ integration for STT MRAM Grant 9,159,910 - Kang , et al. October 13, 2	2015-10-13
Electrically broken, but mechanically continuous die seal for integrated circuits Grant 8,933,567 - Bang , et al. January 13, 2	2015-01-13
Predictive modeling of contact and via modules for advanced on-chip interconnect technology Grant 8,483,997 - Li , et al. July 9, 2	2013-07-09
Intertwined finger capacitors Grant 8,207,569 - Bang June 26, 2	2012-06-26
Electrically Broken, but Mechanically Continuous Die Seal for Integrated Circuits App 20110284994 - Bang; David ; et al.	2011-11-24
Method and apparatus for estimating resistance and capacitance of metal interconnects Grant 7,973,541 - Jayapalan , et al. July 5, 2	2011-07-05
Circuit simulator parameter extraction using a configurable ring oscillator Grant 7,675,372 - Bang , et al. March 9, 2	2010-03-09
Predictive Modeling Of Contact And Via Modules For Advanced On-chip Interconnect Technology App 20100057411 - Li; Xia ; et al.	2010-03-04
One-Mask MTJ Integration for STT MRAM App 20090261433 - Kang; Seung H. ; et al.	2009-10-22
Method And Apparatus For Estimating Resistance And Capacitance Of Metal Interconnects App 20090146681 - Jayapalan; Jayakannan ; et al.	2009-06-11
Intertwined Finger Capacitors App 20080304205 - Bang; David	2008-12-11
Circuit Simulator Parameter Extraction Using a Configurable Ring Oscillator App 20080048790 - Bang; David ; et al.	2008-02-28
Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom Grant 6,268,277 - Bang July 31, 2	2001-07-31
Electron bean curing of low-k dielectrics in integrated circuits Grant 6,169,039 - Lin , et al. January 2, 2	2001-01-02
Method for quantifying ultra-thin dielectric reliability: time dependent dielectric wear-out Grant 6,047,243 - Bang , et al. April 4, 2	2000-04-04
Air voids underneath metal lines to reduce parasitic capacitance Grant 5,953,625 - Bang September 14, 1	1999-09-14
Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process Grant 5,949,143 - Bang September 7, 1	1999-09-07

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