| Patent | Date |
|---|
Method of forming source/drain regions in a semiconductor device
Grant 6,720,227 - Kadosh , et al. April 13, 2 | 2004-04-13 |
Shallow trench isolation formation with ion implantation
Grant 6,599,810 - Kepler , et al. July 29, 2 | 2003-07-29 |
Dielectric having an air gap formed between closely spaced interconnect lines
Grant 6,376,330 - Fulford, Jr. , et al. April 23, 2 | 2002-04-23 |
Semiconductor Isolation Region Bounded By A Trench And Covered With An Oxide To Improve Planarization
App 20010020727 - HAUSE, FRED N. ; et al. | 2001-09-13 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 6,208,015 - Bandyopadhyay , et al. March 27, 2 | 2001-03-27 |
Semiconductor topography employing a shallow trench isolation structure with an improved trench edge
Grant 6,165,906 - Bandyopadhyay , et al. December 26, 2 | 2000-12-26 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer
Grant 6,153,833 - Dawson , et al. November 28, 2 | 2000-11-28 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 6,150,721 - Bandyopadhyay , et al. November 21, 2 | 2000-11-21 |
Integrated circuit having conductors of enhanced cross-sectional area
Grant 6,127,264 - Bandyopadhyay , et al. October 3, 2 | 2000-10-03 |
Dissolvable dielectric method and structure
Grant 6,091,149 - Hause , et al. July 18, 2 | 2000-07-18 |
Shallow trench isolation formation with trench wall spacer
Grant 6,074,927 - Kepler , et al. June 13, 2 | 2000-06-13 |
Stepper alignment mark structure for maintaining alignment integrity
Grant 6,037,671 - Kepler , et al. March 14, 2 | 2000-03-14 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
Grant 6,031,289 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,998,293 - Dawson , et al. December 7, 1 | 1999-12-07 |
Method of planarizing a semiconductor topography using multiple polish pads
Grant 5,968,843 - Dawson , et al. October 19, 1 | 1999-10-19 |
Dissolvable dielectric method
Grant 5,953,626 - Hause , et al. September 14, 1 | 1999-09-14 |
Shallow trench isolation formation with reduced polish stop thickness
Grant 5,930,645 - Lyons , et al. July 27, 1 | 1999-07-27 |
Method for achieving global planarization by forming minimum mesas in large field areas
Grant 5,926,713 - Hause , et al. July 20, 1 | 1999-07-20 |
Method of making an integrated circuit with oxidizable trench liner
Grant 5,926,717 - Michael , et al. July 20, 1 | 1999-07-20 |
Integrated circuit having horizontally and vertically offset interconnect lines
Grant 5,854,131 - Dawson , et al. December 29, 1 | 1998-12-29 |
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
Grant 5,851,913 - Brennan , et al. December 22, 1 | 1998-12-22 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
Grant 5,850,105 - Dawson , et al. December 15, 1 | 1998-12-15 |
Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
Grant 5,847,462 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 5,846,876 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
Grant 5,827,776 - Bandyopadhyay , et al. October 27, 1 | 1998-10-27 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 5,814,555 - Bandyopadhyay , et al. September 29, 1 | 1998-09-29 |
Wafer cleaning procedure useful in the manufacture of a non-volatile memory device
Grant 5,811,334 - Buller , et al. September 22, 1 | 1998-09-22 |
Interlevel dielectric with air gaps to reduce permitivity
Grant 5,792,706 - Michael , et al. August 11, 1 | 1998-08-11 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,783,864 - Dawson , et al. July 21, 1 | 1998-07-21 |
Semiconductor interlevel dielectric having a polymide for producing air gaps
Grant 5,783,481 - Brennan , et al. July 21, 1 | 1998-07-21 |
Method of forming a recessed interconnect structure
Grant 5,767,012 - Fulford, Jr. , et al. June 16, 1 | 1998-06-16 |
Method of formation of an air gap within a semiconductor dielectric by solvent desorption
Grant 5,759,913 - Fulford, Jr. , et al. June 2, 1 | 1998-06-02 |
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