BAN; Hyo-Dong

Patent Applications and Registrations

Patent applications and USPTO patent grants for BAN; Hyo-Dong.The latest application filed is for "methods of manufacturing devices including a buried gate cell and a bit line structure including a thermal oxide buffer pattern".

Company Profile

0.10.10

BAN; Hyo-Dong - Suwon-si KR
Ban; Hyo-Dong - Gyeonggi-do KR
Ban; Hyo-dong - Suwon KR
Ban, Hyo-Dong - Suwon-city KR
Ban, Hyo-Dong - Kyonggi-do KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods Of Manufacturing Devices Including A Buried Gate Cell And A Bit Line Structure Including A Thermal Oxide Buffer Pattern App 20210091086 - HONG; Augustin Jinwoo ; et al.	2021-03-25
Methods of manufacturing devices including a buried gate cell and a bit line structure including a thermal oxide buffer pattern Grant 10,886,277 - Hong , et al. January 5, 2	2021-01-05
Memory Devices And Methods Of Manufacturing The Same App 20190139963 - HONG; Augustin Jinwoo ; et al.	2019-05-09
Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film Grant RE46,549 - Minn , et al. September 12, 2	2017-09-12
Semiconductor devices including guard ring structures Grant 8,928,073 - Jang , et al. January 6, 2	2015-01-06
Semiconductor Devices Including Guard Ring Structures App 20130248997 - Jang; Se-myeong ; et al.	2013-09-26
Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip Grant 7,667,331 - Lim , et al. February 23, 2	2010-02-23
Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip App 20090014895 - Lim; Jong-Seok ; et al.	2009-01-15
Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Grant 7,339,223 - Lee , et al. March 4, 2	2008-03-04
Semiconductor Devices Having Dual Capping Layer Patterns And Methods Of Manufacturing The Same App 20060231903 - LEE; Hoo-Ouk ; et al.	2006-10-19
Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Grant 7,081,389 - Lee , et al. July 25, 2	2006-07-25
Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same Grant 6,835,998 - Lee , et al. December 28, 2	2004-12-28
Semiconductor devices having dual capping layer patterns and methods of manufacturing the same App 20040183101 - Lee, Ho-Ouk ; et al.	2004-09-23
Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film Grant 6,696,353 - Minn , et al. February 24, 2	2004-02-24
Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film App 20030181045 - Minn, Eun-Young ; et al.	2003-09-25
Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film Grant 6,566,735 - Minn , et al. May 20, 2	2003-05-20
Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same App 20020179998 - Lee, Chi-Hoon ; et al.	2002-12-05
Method of forming fuse area structure including protection film on sidewall of fuse opening in semiconductor device Grant 6,448,113 - Lee , et al. September 10, 2	2002-09-10
Contact forming method for semiconductor device App 20020068423 - Park, Young-Hoon ; et al.	2002-06-06
Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same App 20010005604 - Lee, Chi-hoon ; et al.	2001-06-28

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