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Long instruction word controlling plural independent processor operations
Grant RE44,190 - Guttag , et al. April 30, 2 | 2013-04-30 |
Long instruction word controlling plural independent processor operations
Grant 7,389,317 - Guttag , et al. June 17, 2 | 2008-06-17 |
Long Instruction Word Controlling Plural Independent Processor Operations
App 20080077771 - Guttag; KarlM ; et al. | 2008-03-27 |
Transfer request bus node for transfer controller with hub and ports
Grant 7,047,284 - Agarwala , et al. May 16, 2 | 2006-05-16 |
System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data
Grant 7,039,795 - Balmer , et al. May 2, 2 | 2006-05-02 |
Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware
Grant 6,948,050 - Gove , et al. September 20, 2 | 2005-09-20 |
Data processing apparatus with register file bypass
Grant 6,839,831 - Balmer , et al. January 4, 2 | 2005-01-04 |
Data processing system with register store/load utilizing data packing/unpacking
Grant 6,829,696 - Balmer , et al. December 7, 2 | 2004-12-07 |
Batch method for accessing IDE device task registers
Grant 6,757,775 - Balmer June 29, 2 | 2004-06-29 |
Data processing apparatus with indirect register file access
Grant 6,754,809 - Guttag , et al. June 22, 2 | 2004-06-22 |
Microprocessor with instructions for shuffling and dealing data
Grant 6,745,319 - Balmer , et al. June 1, 2 | 2004-06-01 |
Data processor with flexible multiply unit
Grant 6,711,602 - Bhandal , et al. March 23, 2 | 2004-03-23 |
System and method for processing data using a multiplexing architecture
App 20030233529 - Balmer, Keith ; et al. | 2003-12-18 |
Method and apparatus for data transfer employing closed loop of memory nodes
Grant 6,654,834 - Robertson , et al. November 25, 2 | 2003-11-25 |
Long instruction word controlling plural independent processor operations
App 20030105793 - Guttag, Karl M. ; et al. | 2003-06-05 |
Data processing apparatus with register file bypass
App 20020108026 - Balmer, Keith ; et al. | 2002-08-08 |
Batch method for accessing IDE device task registers
App 20020065995 - Balmer, Keith | 2002-05-30 |
Long instruction word controlling plural independent processor operations
Grant 6,370,558 - Guttag , et al. April 9, 2 | 2002-04-09 |
Single integrated circuit embodying a risc processor and a digital signal processor
Grant 6,260,088 - Gove , et al. July 10, 2 | 2001-07-10 |
Long instruction word controlling plural independent processor operations
Grant 6,240,437 - Guttag , et al. May 29, 2 | 2001-05-29 |
Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
Grant 6,185,629 - Simpson , et al. February 6, 2 | 2001-02-06 |
Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result
Grant 6,173,394 - Guttag , et al. January 9, 2 | 2001-01-09 |
Three input arithmetic logic unit with barrel rotator
Grant 6,116,768 - Guttag , et al. September 12, 2 | 2000-09-12 |
Three input arithmetic logic unit with shifter
Grant 6,098,163 - Guttag , et al. August 1, 2 | 2000-08-01 |
System and method of memory access in apparatus having plural processors and plural memories
Grant 6,070,003 - Gove , et al. May 30, 2 | 2000-05-30 |
Synchronized MIMD multi-processing system and method of operation
Grant 6,038,584 - Balmer March 14, 2 | 2000-03-14 |
Long instruction word controlling plural independent processor operations
Grant 6,032,170 - Guttag , et al. February 29, 2 | 2000-02-29 |
Three input arithmetic logic unit with shifter and/or mask generator
Grant 5,995,748 - Guttag , et al. November 30, 1 | 1999-11-30 |
Three input arithmetic logic unit with shifter and mask generator
Grant 5,974,539 - Guttag , et al. October 26, 1 | 1999-10-26 |
Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors while one processor services an interrupt
Grant 5,933,624 - Balmer August 3, 1 | 1999-08-03 |
Pipelined data processing including program counter recycling
Grant 5,922,070 - Swoboda , et al. July 13, 1 | 1999-07-13 |
Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor
Grant 5,881,272 - Balmer March 9, 1 | 1999-03-09 |
Synchronized MIMD multi-processing system and method inhibiting instruction fetch on memory access stall
Grant 5,809,288 - Balmer September 15, 1 | 1998-09-15 |
Arithmetic logic unit with conditional register source selection
Grant 5,805,913 - Guttag , et al. September 8, 1 | 1998-09-08 |
Reduced area of crossbar and method of operation
Grant 5,768,609 - Gove , et al. June 16, 1 | 1998-06-16 |
Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
Grant 5,761,726 - Guttag , et al. June 2, 1 | 1998-06-02 |
Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register
Grant 5,758,195 - Balmer May 26, 1 | 1998-05-26 |
Long instruction word controlling plural independent processor operations
Grant 5,742,538 - Guttag , et al. April 21, 1 | 1998-04-21 |
Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections
Grant 5,734,880 - Guttag , et al. March 31, 1 | 1998-03-31 |
Message passing and blast interrupt from processor
Grant 5,724,599 - Balmer , et al. March 3, 1 | 1998-03-03 |
Pipelined data processing including interrupts
Grant 5,724,566 - Swoboda , et al. March 3, 1 | 1998-03-03 |
Data communications system with address remapping for expanded external memory access
Grant 5,715,419 - Szczepanek , et al. February 3, 1 | 1998-02-03 |
Memory store from a selected one of a register pair conditional upon the state of a selected status bit
Grant 5,696,959 - Guttag , et al. December 9, 1 | 1997-12-09 |
Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor
Grant 5,696,913 - Gove , et al. December 9, 1 | 1997-12-09 |
Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input
Grant 5,696,954 - Guttag , et al. December 9, 1 | 1997-12-09 |
Guided transfers with variable stepping
Grant 5,651,127 - Gove , et al. July 22, 1 | 1997-07-22 |
Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section
Grant 5,640,578 - Balmer , et al. June 17, 1 | 1997-06-17 |
Three input arithmetic logic unit with controllable shifter and mask generator
Grant 5,634,065 - Guttag , et al. May 27, 1 | 1997-05-27 |
Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors
Grant 5,613,146 - Gove , et al. March 18, 1 | 1997-03-18 |
Address generator with controllable modulo power of two addressing capability
Grant 5,606,520 - Gove , et al. February 25, 1 | 1997-02-25 |
Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
Grant 5,606,677 - Balmer , et al. February 25, 1 | 1997-02-25 |
Three input arithmetic logic unit with mask generator
Grant 5,600,847 - Guttag , et al. February 4, 1 | 1997-02-04 |
Multiple operations employing divided arithmetic logic unit and multiple flags register
Grant 5,592,405 - Gove , et al. January 7, 1 | 1997-01-07 |
Three input arithmetic logic unit with mask generator
Grant 5,590,350 - Guttag , et al. December 31, 1 | 1996-12-31 |
Architecture of transfer processor
Grant 5,524,265 - Balmer , et al. June 4, 1 | 1996-06-04 |
Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
Grant 5,522,083 - Gove , et al. May 28, 1 | 1996-05-28 |
Long instruction word controlling plural independent processor operations
Grant 5,509,129 - Guttag , et al. April 16, 1 | 1996-04-16 |
Plural memory access address generation employing guide table entries forming linked list
Grant 5,487,146 - Guttag , et al. January 23, 1 | 1996-01-23 |
Multi-processor with crossbar link of processors and memories and method of operation
Grant 5,471,592 - Gove , et al. November 28, 1 | 1995-11-28 |
Multi-processor having control over synchronization of processors in mind mode and method of operation
Grant 5,371,896 - Gove , et al. December 6, 1 | 1994-12-06 |
Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data
Grant 5,339,447 - Balmer August 16, 1 | 1994-08-16 |
Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode
Grant 5,239,654 - Ing-Simmons , et al. August 24, 1 | 1993-08-24 |
Switch matrix having integrated crosspoint logic and method of operation
Grant 5,226,125 - Balmer , et al. July 6, 1 | 1993-07-06 |
Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
Grant 5,212,777 - Gove , et al. May 18, 1 | 1993-05-18 |
Sliced addressing multi-processor and method of operation
Grant 5,197,140 - Balmer March 23, 1 | 1993-03-23 |
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