Balasubramanian; Suresh
Patent Applications and Registrations
Patent applications and USPTO patent grants for Balasubramanian; Suresh.The latest application filed is for "clock duty cycle correction".
Company Profile
6.23.23
- Balasubramanian; Suresh - Cupertino CA
- Balasubramanian; Suresh - Dallas TX
- BALASUBRAMANIAN; Suresh - Sunnyvale CA
- Balasubramanian; Suresh - Shrewsbury MA
- Balasubramanian; Suresh - Richardson TX
- Balasubramanian; Suresh - Coimbatore IN
- Balasubramanian; Suresh - Coimbatore TamilNadu IN
Patent Activity
| Patent | Date |
|---|---|
| Hybrid pulse/two-stage data latch Grant 11,418,173 - Venugopal , et al. August 16, 2 | 2022-08-16 |
| Clock Duty Cycle Correction App 20220103166 - Balasubramanian; Suresh ; et al. | 2022-03-31 |
| Methods and apparatus to improve performance while reading a one-time-programmable memory Grant 11,170,864 - Balasubramanian , et al. November 9, 2 | 2021-11-09 |
| Methods and apparatus to improve performance while reading a one-time programmable memory Grant 11,145,378 - Balasubramanian , et al. October 12, 2 | 2021-10-12 |
| Hybrid Pulse/Two-Stage Data Latch App 20200373915 - Venugopal; Vivekanandan ; et al. | 2020-11-26 |
| Methods And Apparatus To Improve Performance While Reading A One-time-programmable Memory App 20200265906 - Balasubramanian; Suresh ; et al. | 2020-08-20 |
| Methods And Apparatus To Improve Performance While Reading A One-time Programmable Memory App 20200265907 - Balasubramanian; Suresh ; et al. | 2020-08-20 |
| Hybrid pulse/master-slave data latch Grant 10,742,201 - Venugopal , et al. A | 2020-08-11 |
| Hybrid Pulse/master-slave Data Latch App 20200106425 - Venugopal; Vivekanandan ; et al. | 2020-04-02 |
| End-to-end Sales Workflow Acceleration Systems And Methods App 20180204226 - BALASUBRAMANIAN; Suresh ; et al. | 2018-07-19 |
| Systems And Methods For Improving Sales Process Workflow App 20180101797 - Mueller; Frederick Lloyd ; et al. | 2018-04-12 |
| Frequency division clock alignment Grant 9,417,655 - Balasubramanian , et al. August 16, 2 | 2016-08-16 |
| Frequency division clock alignment using pattern selection Grant 9,411,361 - Balasubramanian , et al. August 9, 2 | 2016-08-09 |
| Frequency Division Clock Alignment App 20160142066 - Balasubramanian; Suresh ; et al. | 2016-05-19 |
| Frequency Division Clock Alignment Using Pattern Selection App 20160142067 - Balasubramanian; Suresh ; et al. | 2016-05-19 |
| Clock distribution circuit with distributed delay locked loop Grant 9,335,784 - Balasubramanian May 10, 2 | 2016-05-10 |
| Multi-function delay locked loop Grant 9,306,584 - Lin , et al. April 5, 2 | 2016-04-05 |
| Scannable flop with a single storage element Grant 9,264,023 - Balasubramanian February 16, 2 | 2016-02-16 |
| Multi-function delay locked loop Grant 9,143,140 - Lin , et al. September 22, 2 | 2015-09-22 |
| Multiplexer flop Grant 9,130,549 - Balasubramanian , et al. September 8, 2 | 2015-09-08 |
| Multi-Function Delay Locked Loop App 20150188528 - Lin; David ; et al. | 2015-07-02 |
| Clock Gated Delay Line Based On Setting Value App 20150061743 - Balasubramanian; Suresh | 2015-03-05 |
| Distributed Delay Locked Loop App 20150067383 - Balasubramanian; Suresh | 2015-03-05 |
| Multiplexer Flop App 20150061741 - Balasubramanian; Suresh ; et al. | 2015-03-05 |
| Scannable Flop With A Single Storage Element App 20150061740 - Balasubramanian; Suresh | 2015-03-05 |
| Clock gated delay line based on setting value Grant 8,963,601 - Balasubramanian February 24, 2 | 2015-02-24 |
| State machine for deskew delay locked loop Grant 8,513,994 - Balasubramanian August 20, 2 | 2013-08-20 |
| Low-power redundancy for non-volatile memory Grant 8,381,075 - Toops , et al. February 19, 2 | 2013-02-19 |
| State Machine For Deskew Delay Locked Loop App 20120206178 - Balasubramanian; Suresh | 2012-08-16 |
| Multi-function Delay Locked Loop App 20120206181 - Lin; David ; et al. | 2012-08-16 |
| Low-Power Redundancy for Non-Volatile Memory App 20110231736 - Toops; David J. ; et al. | 2011-09-22 |
| High performance, area efficient direct bitline sensing circuit Grant 7,684,274 - Rengarajan , et al. March 23, 2 | 2010-03-23 |
| Deterministic operation of an input/output interface Grant 7,568,118 - Anderson , et al. July 28, 2 | 2009-07-28 |
| Novel High Performance, Area Efficient Direct Bitline Sensing Circuit App 20090147605 - Rengarajan; Krishnan S. ; et al. | 2009-06-11 |
| Dual port memory unit using a single port memory core Grant 7,349,285 - Balasubramanian , et al. March 25, 2 | 2008-03-25 |
| Deterministic operation of an input/output interface App 20070067514 - Anderson; Warren R. ; et al. | 2007-03-22 |
| Dual Port Memory Unit Using a Single Port Memory Core App 20060171239 - BALASUBRAMANIAN; Suresh ; et al. | 2006-08-03 |
| Tracking circuit enabling quick/accurate retrieval of data stored in a memory array Grant 7,016,245 - Balasubramanian , et al. March 21, 2 | 2006-03-21 |
| Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal Grant 7,015,727 - Balasubramanian March 21, 2 | 2006-03-21 |
| Sense amplifier for a memory array Grant 7,012,846 - Balasubramanian , et al. March 14, 2 | 2006-03-14 |
| Tracking circuit enabling quick/accurate retrieval of data stored in a memory array App 20050169078 - Balasubramanian, Suresh ; et al. | 2005-08-04 |
| Sense amplifier for a memory array App 20050169077 - Balasubramanian, Suresh ; et al. | 2005-08-04 |
| Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal App 20030112913 - Balasubramanian, Suresh | 2003-06-19 |
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