loadpatents
name:-0.017263889312744
name:-0.012917995452881
name:-0.00055289268493652
Balasubramanian; Narayanan Patent Filings

Balasubramanian; Narayanan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Balasubramanian; Narayanan.The latest application filed is for "nanowire sensor, nanowire sensor array and method of fabricating the same".

Company Profile
0.11.13
  • Balasubramanian; Narayanan - Singapore SG
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Nanowire sensor, nanowire sensor array and method of fabricating the same
Grant 8,236,595 - Agarwal , et al. August 7, 2
2012-08-07
Nanowire Sensor, Nanowire Sensor Array And Method Of Fabricating The Same
App 20110193183 - Agarwal; Ajay ;   et al.
2011-08-11
Fully salicided (FUCA) MOSFET structure
Grant 7,682,914 - Lo , et al. March 23, 2
2010-03-23
Transparent Microfluidic Device
App 20100055673 - Agarwal; Ajay ;   et al.
2010-03-04
Method of fabricating tensile strained layers and compressive strain layers for a CMOS device
Grant 7,439,165 - Lo , et al. October 21, 2
2008-10-21
Method to reduce junction leakage current in strained silicon on silicon-germanium devices
Grant 7,425,751 - Balasubramanian , et al. September 16, 2
2008-09-16
Gate electrode architecture for improved work function tuning and method of manufacture
Grant 7,397,090 - Mathew , et al. July 8, 2
2008-07-08
Fully salicided (FUCA) MOSFET structure
App 20080064153 - Qiang Lo; Patrick Guo ;   et al.
2008-03-13
Fully salicided (FUSA) MOSFET structure
Grant 7,294,890 - Lo , et al. November 13, 2
2007-11-13
Method of fabricating strained channel devices
App 20060226483 - Lo; Patrick Guo Oiang ;   et al.
2006-10-12
Fully salicided (FUSA) MOSFET structure
App 20060199321 - Lo; Patrick Guo Qiang ;   et al.
2006-09-07
Gate Electrode Architecture for Improved Work Function Tuning and Method of Manufacture
App 20050275035 - Mathew, Shajan ;   et al.
2005-12-15
Method to reduce junction leakage current in strained silicon on silicon-germanium devices
App 20050130361 - Balasubramanian, Narayanan ;   et al.
2005-06-16
CMOS compatible low band offset double barrier resonant tunneling diode
App 20050056827 - Li, Ming Fu ;   et al.
2005-03-17
Method to reduce junction leakage current in strained silicon on silicon-germanium devices
Grant 6,846,720 - Balasubramanian , et al. January 25, 2
2005-01-25
Method To Reduce Junction Leakage Current In Strained Silicon On Silicon-germanium Devices
App 20040259314 - Balasubramanian, Narayanan ;   et al.
2004-12-23
Method of fabricating a CMOS device with dual metal gate electrodes
App 20040245578 - Park, Chang Seo ;   et al.
2004-12-09
Stacked LDD high frequency LDMOSFET
Grant 6,664,596 - Cai , et al. December 16, 2
2003-12-16
Stacked LDD high frequency LDMOSFET
App 20030085448 - Cai, Jun ;   et al.
2003-05-08
Process for device using partial SOI
App 20030040185 - Jun, Cai ;   et al.
2003-02-27
Stacked LDD high frequency LDMOSFET
App 20020164844 - Cai, Jun ;   et al.
2002-11-07
Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner
Grant 6,468,853 - Balasubramanian , et al. October 22, 2
2002-10-22
Method to form gate oxides of different thicknesses on a silicon substrate
Grant 6,235,591 - Balasubramanian , et al. May 22, 2
2001-05-22
Method for forming a low impurity diffusion polysilicon layer
Grant 5,767,004 - Balasubramanian , et al. June 16, 1
1998-06-16

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