| Patent | Date |
|---|
First order memory-less dynamic element matching technique
Grant 11,417,371 - Bal , et al. August 16, 2 | 2022-08-16 |
Clock and data recovery circuit
Grant 11,411,565 - Singh , et al. August 9, 2 | 2022-08-09 |
Data Bridge For Interfacing Source Synchronous Datapaths With Unknown Clock Phases
App 20220206987 - BAL; Ankur ; et al. | 2022-06-30 |
Method And Architecture For Serial Link Characterization By Arbitrary Size Pattern Generator
App 20220188203 - BAL; Ankur ; et al. | 2022-06-16 |
DC-AC converter
Grant 11,336,194 - Singh , et al. May 17, 2 | 2022-05-17 |
High Speed Data Weighted Averaging (dwa) To Binary Converter Circuit
App 20220069837 - BAL; Ankur ; et al. | 2022-03-03 |
High Throughput Linear Feedback Shift Register
App 20220066498 - BAL; Ankur ; et al. | 2022-03-03 |
Method And Device For Testing Successive Approximation Register Analog-to-digital Converters
App 20220006467 - BAL; Ankur ; et al. | 2022-01-06 |
Timing Skew Mismatch Calibration For Time Interleaved Analog To Digital Converters
App 20210409032 - BAL; Ankur ; et al. | 2021-12-30 |
Debounce circuit with noise immunity and glitch event tracking
Grant 11,177,799 - Bal , et al. November 16, 2 | 2021-11-16 |
Sigma-delta Analog-to-digital Converter Circuit With Real Time Correction For Digital-to-analog Converter Mismatch Error
App 20210351780 - BAL; Ankur ; et al. | 2021-11-11 |
First Order Memory-less Dynamic Element Matching Technique
App 20210343319 - BAL; Ankur ; et al. | 2021-11-04 |
Clock Delay Circuit For Chip Reset Architecture
App 20210286417 - BAL; Ankur ; et al. | 2021-09-16 |
Digital sinusoid generator
Grant 11,092,993 - Bal , et al. August 17, 2 | 2021-08-17 |
First order memory-less dynamic element matching technique
Grant 11,094,354 - Bal , et al. August 17, 2 | 2021-08-17 |
Clock And Data Recovery Circuit
App 20210211133 - SINGH; Rupesh ; et al. | 2021-07-08 |
Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter
Grant 11,043,960 - Bal , et al. June 22, 2 | 2021-06-22 |
High Throughput Digital Filter Architecture For Processing Unary Coded Data
App 20210133124 - BAL; Ankur ; et al. | 2021-05-06 |
Debounce Circuit With Noise Immunity And Glitch Event Tracking
App 20210119621 - Bal; Ankur ; et al. | 2021-04-22 |
First Order Memory-less Dynamic Element Matching Technique
App 20210110852 - BAL; Ankur ; et al. | 2021-04-15 |
High Throughput Parallel Architecture For Recursive Sinusoid Synthesizer
App 20210081174 - BAL; Ankur ; et al. | 2021-03-18 |
Programmable delay circuit
Grant 10,944,387 - Bal , et al. March 9, 2 | 2021-03-09 |
Programmable Delay Circuit
App 20200395926 - BAL; Ankur ; et al. | 2020-12-17 |
Sigma-delta Analog-to-digital Converter Circuit With Correction For Mismatch Error Introduced By The Feedback Digital-to-analog Converter
App 20200389180 - BAL; Ankur ; et al. | 2020-12-10 |
Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator
Grant 10,862,503 - Bal , et al. December 8, 2 | 2020-12-08 |
Clock Jitter Measurement Using Signal-to-noise Ratio Degradation In A Continuous Time Delta-sigma Modulator
App 20200186162 - BAL; Ankur ; et al. | 2020-06-11 |
Digital Sinusoid Generator
App 20190384347 - BAL; Ankur ; et al. | 2019-12-19 |
Cascaded Integrator-comb (cic) Decimation Filter With Integration Reset To Support A Reduced Number Of Differentiators
App 20190379358 - BAL; Ankur ; et al. | 2019-12-12 |
Glitch immune cascaded integrator comb architecture for higher order signal interpolation
Grant 10,498,312 - Singh , et al. De | 2019-12-03 |
Latency buffer circuit with adaptable time shift
Grant 10,484,165 - Singh , et al. Nov | 2019-11-19 |
Latency Buffer Circuit With Adaptable Time Shift
App 20190190688 - Singh; Rupesh ; et al. | 2019-06-20 |
Glitch Immune Cascaded Integrator Comb Architecture For Higher Order Signal Interpolation
App 20190158070 - Singh; Mohit ; et al. | 2019-05-23 |
High speed data weighted averaging architecture
Grant 10,218,380 - Bal , et al. Feb | 2019-02-26 |
High speed data weighted averaging architecture
Grant 10,211,850 - Bal , et al. Feb | 2019-02-19 |
High speed data weighted averaging architecture
Grant 10,050,640 - Bal , et al. August 14, 2 | 2018-08-14 |
Polyphase decimation FIR filters and methods
Grant 10,050,607 - Bhargava , et al. August 14, 2 | 2018-08-14 |
Decimation FIR filters and methods
Grant 10,050,606 - Bhargava , et al. August 14, 2 | 2018-08-14 |
Noise removal system
Grant 9,858,913 - Bal , et al. January 2, 2 | 2018-01-02 |
Polyphase Decimation Fir Filters And Methods
App 20170294898 - Bhargava; Neha ; et al. | 2017-10-12 |
Apparatus for built-in self-test (BIST) of a Nyquist rate analog-to-digital converter (ADC) circuit
Grant 9,780,803 - Bal , et al. October 3, 2 | 2017-10-03 |
Noise Removal System
App 20170249931 - Bal; Ankur ; et al. | 2017-08-31 |
Noise removal system
Grant 9,685,150 - Bal , et al. June 20, 2 | 2017-06-20 |
Self-calibrated digital-to-analog converter
Grant 9,379,728 - Singh , et al. June 28, 2 | 2016-06-28 |
Polyphase Decimation Fir Filters And Methods
App 20160182014 - Bhargava; Neha ; et al. | 2016-06-23 |
Methods and apparatus for offline mismatch removal in sigma delta analog-to-digital converters
Grant 9,246,509 - Bhargava , et al. January 26, 2 | 2016-01-26 |
Signal synchronizing systems and methods
Grant 9,225,321 - Bal , et al. December 29, 2 | 2015-12-29 |
Apparatus for signal processing
Grant 9,015,219 - Bal , et al. April 21, 2 | 2015-04-21 |
Low latency filter
Grant 8,878,710 - Bal , et al. November 4, 2 | 2014-11-04 |
Noise Removal System
App 20140241539 - BAL; Ankur ; et al. | 2014-08-28 |
Glitch free dynamic element matching scheme
Grant 8,803,718 - Parida , et al. August 12, 2 | 2014-08-12 |
Offset-free sinc interpolator and related methods
Grant 8,738,679 - Parida , et al. May 27, 2 | 2014-05-27 |
Noise removal system
Grant 8,731,214 - Bal , et al. May 20, 2 | 2014-05-20 |
Low Latency Filter
App 20140132434 - BAL; Ankur ; et al. | 2014-05-15 |
Filter block for compensating droop in a frequency response of a signal
Grant 8,645,445 - Bal , et al. February 4, 2 | 2014-02-04 |
Apparatus For Signal Processing
App 20130110898 - BAL; Ankur ; et al. | 2013-05-02 |
Glitch Free Dynamic Element Matching Scheme
App 20120176264 - PARIDA; Rakhel Kumar ; et al. | 2012-07-12 |
Signal Synchronizing Systems And Methods
App 20120166856 - BAL; Ankur ; et al. | 2012-06-28 |
Glitch free dynamic element matching scheme
Grant 8,159,381 - Parida , et al. April 17, 2 | 2012-04-17 |
Glitch Free Dynamic Element Matching Scheme
App 20110279292 - Parida; Rakhel Kumar ; et al. | 2011-11-17 |
Noise Removal System
App 20110142254 - BAL; Ankur ; et al. | 2011-06-16 |
Offset-free Sinc Interpolator And Related Methods
App 20110004647 - PARIDA; Rakhel Kumar ; et al. | 2011-01-06 |
Integrated circuit including at least one configurable logic cell capable of multiplication
Grant 7,856,467 - Swami , et al. December 21, 2 | 2010-12-21 |
Method for sharing configuration data for high logic density on chip
Grant RE41,561 - Bal August 24, 2 | 2010-08-24 |
Filter Block for Compensating Droop in a Frequency Response of a Signal
App 20100121897 - Bal; Ankur ; et al. | 2010-05-13 |
Efficient latch array initialization
Grant 7,180,792 - Bal , et al. February 20, 2 | 2007-02-20 |
Integrated circuit including at least one configurable logic cell capable of multiplication
App 20060195503 - Swami; Parvesh ; et al. | 2006-08-31 |
Method for sharing configuration data for high logic density on chip
Grant 7,038,489 - Bal May 2, 2 | 2006-05-02 |
High performance interconnect architecture for field programmable gate arrays
Grant 7,030,648 - Bal , et al. April 18, 2 | 2006-04-18 |
FPGA peripheral routing with symmetric edge termination at FPGA boundaries
Grant 6,888,374 - Bal May 3, 2 | 2005-05-03 |
High performance interconnect architecture for field programmable gate arrays
App 20040178821 - Bal, Ankur ; et al. | 2004-09-16 |
System for simplifying the programmable memory to logic interface in FPGA
Grant 6,748,577 - Bal June 8, 2 | 2004-06-08 |
FPGA peripheral routing with symmetric edge termination at FPGA boundaries
App 20040036499 - Bal, Ankur | 2004-02-26 |
Efficient latch array initialization
App 20030223298 - Bal, Ankur ; et al. | 2003-12-04 |
Programmable logic device including bi-directional shift register
Grant 6,646,465 - Bal November 11, 2 | 2003-11-11 |
System for rapid configuration of a programmable logic device
Grant 6,642,743 - Bal November 4, 2 | 2003-11-04 |
Concurrent logic operations using decoder circuitry of a look-up table
Grant 6,624,771 - Bal September 23, 2 | 2003-09-23 |
System for simplifying the programmable memory to logic interface in FPGA
App 20030005402 - Bal, Ankur | 2003-01-02 |
Method for sharing configuration data for high logic density on chip
App 20020194449 - Bal, Ankur | 2002-12-19 |
Concurrent logic operations using decoder circuitry of a look-up table
App 20020175703 - Bal, Ankur | 2002-11-28 |
Programmable logic device including bi-directional shift register
App 20020113618 - Bal, Ankur | 2002-08-22 |
System for rapid configuration of a programmable logic device
App 20020114200 - Bal, Ankur | 2002-08-22 |
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