Baker; Faye D.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Baker; Faye D..The latest application filed is for "variable performance ranking and modification in design for manufacturability of circuits".
- Baker; Faye D. - Burlington VT
- Baker; Faye D - Burlington VT
| Patent | Date |
|---|---|
| Variable performance ranking and modification in design for manufacturability of circuits Grant 7,823,106 - Baker , et al. October 26, 2 | 2010-10-26 |
| IC layout optimization to improve yield Grant 7,818,694 - Allen , et al. October 19, 2 | 2010-10-19 |
| Variable Performance Ranking and Modification in Design for Manufacturability of Circuits App 20090235214 - Baker; Faye D. ; et al. | 2009-09-17 |
| IC Layout Optimization to Improve Yield App 20090100386 - Allen; Robert J. ; et al. | 2009-04-16 |
| IC layout optimization to improve yield Grant 7,503,020 - Allen , et al. March 10, 2 | 2009-03-10 |
| IC Layout Optimization To Improve Yield App 20070294648 - Allen; Robert J. ; et al. | 2007-12-20 |
| Backside protection films Grant 6,670,283 - Baker , et al. December 30, 2 | 2003-12-30 |
| Backside protection films App 20030096507 - Baker, Faye D. ; et al. | 2003-05-22 |
| Method and structure to reduce latch-up using edge implants Grant 5,861,330 - Baker , et al. January 19, 1 | 1999-01-19 |
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