loadpatents
name:-0.0067288875579834
name:-0.049153089523315
name:-0.0014269351959229
Bahl; Swapnil Patent Filings

Bahl; Swapnil

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bahl; Swapnil.The latest application filed is for "scan compression architecture for highly compressed designs and associated methods".

Company Profile
1.16.13
  • Bahl; Swapnil - New Delhi IN
  • Bahl; Swapnil - Greater Noida IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scan compression architecture for highly compressed designs and associated methods
Grant 10,354,742 - Bahl , et al. July 16, 2
2019-07-16
Scan Compression Architecture For Highly Compressed Designs And Associated Methods
App 20170140838 - Bahl; Swapnil ;   et al.
2017-05-18
Scan compression architecture for highly compressed designs and associated methods
Grant 9,606,180 - Bahl , et al. March 28, 2
2017-03-28
Synchronous on-chip clock controllers
Grant 9,264,049 - Bahl , et al. February 16, 2
2016-02-16
Monitoring on-chip clock control during integrated circuit testing
Grant 9,234,938 - Khullar , et al. January 12, 2
2016-01-12
Scan Compression Architecture For Highly Compressed Designs And Associated Methods
App 20150323593 - BAHL; Swapnil ;   et al.
2015-11-12
Monitoring On-chip Clock Control During Integrated Circuit Testing
App 20150323594 - KHULLAR; Shray ;   et al.
2015-11-12
Synchronous On-chip Clock Controllers
App 20150137862 - Bahl; Swapnil ;   et al.
2015-05-21
Integrated circuit with reduced power consumption in a test mode, and related methods
Grant 8,917,123 - Bahl , et al. December 23, 2
2014-12-23
Integrated Circuit With Reduced Power Consumption In A Test Mode, And Related Methods
App 20140292385 - BAHL; SWAPNIL ;   et al.
2014-10-02
Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing
Grant 8,775,857 - Khullar , et al. July 8, 2
2014-07-08
Testing of multi-clock domains
Grant 8,527,824 - Bahl , et al. September 3, 2
2013-09-03
Testing Of Multi-clock Domains
App 20130159802 - BAHL; Swapnil ;   et al.
2013-06-20
Method and apparatus for testing of a memory with redundancy elements
Grant 8,458,545 - Roy , et al. June 4, 2
2013-06-04
Testing of multi-clock domains
Grant 8,381,051 - Bahl , et al. February 19, 2
2013-02-19
Sequential On-chip Clock Controller With Dynamic Bypass For Multi-clock Domain Testing
App 20120166860 - Khullar; Shray ;   et al.
2012-06-28
Method And Apparatus For Testing Of A Memory With Redundancy Elements
App 20120137188 - Roy; Tanmoy ;   et al.
2012-05-31
Testing Of Multi-clock Domains
App 20110264971 - Bahl; Swapnil ;   et al.
2011-10-27
Self programmable shared bist for testing multiple memories
Grant 7,814,385 - Bahl October 12, 2
2010-10-12
On-chip storage memory for storing variable data bits
Grant 7,372,755 - Bahl , et al. May 13, 2
2008-05-13
On-chip and at-speed tester for testing and characterization of different types of memories
Grant 7,353,442 - Bahl , et al. April 1, 2
2008-04-01
Self Programmable Shared Bist For Testing Multiple Memories
App 20080059850 - Bahl; Swapnil
2008-03-06
Configurable length first-in first-out memory
Grant 7,321,520 - Bahl , et al. January 22, 2
2008-01-22
Configurable length first-in first-out memory
App 20060256636 - Bahl; Swapnil ;   et al.
2006-11-16
On-chip and at-speed tester for testing and characterization of different types of memories
App 20050246602 - Bahl, Swapnil ;   et al.
2005-11-03
On-chip storage memory for storing variable data bits
App 20050232028 - Bahl, Swapnil ;   et al.
2005-10-20

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