Baeckler; Gregg William

Patent Applications and Registrations

Patent applications and USPTO patent grants for Baeckler; Gregg William.The latest application filed is for "machine learning training architecture for programmable devices".

Company Profile

24.75.32

Baeckler; Gregg William - San Jose CA
Baeckler; Gregg William - Santa Clara CA
Baeckler; Gregg William - San Francisco CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Deterministic clustering and packing method for random logic on programmable integrated circuits Grant 11,301,611 - Baeckler , et al. April 12, 2	2022-04-12
Machine Learning Training Architecture For Programmable Devices App 20220107783 - Langhammer; Martin ; et al.	2022-04-07
Circuitry for low-precision deep learning Grant 11,275,998 - Langhammer , et al. March 15, 2	2022-03-15
Method and apparatus for performing field programmable gate array packing with continuous carry chains Grant 11,216,249 - Langhammer , et al. January 4, 2	2022-01-04
Machine learning training architecture for programmable devices Grant 11,210,063 - Langhammer , et al. December 28, 2	2021-12-28
Programmable-logic-directed multiplier mapping Grant 11,163,530 - Langhammer , et al. November 2, 2	2021-11-02
Programmable Logic Device With Fine-grained Disaggregation App 20210328589 - Subbareddy; Dheeraj ; et al.	2021-10-21
Method and apparatus for performing synthesis for field programmable gate array embedded feature placement Grant 11,080,019 - Langhammer , et al. August 3, 2	2021-08-03
Programmable logic device with fine-grained disaggregation Grant 11,070,209 - Subbareddy , et al. July 20, 2	2021-07-20
Vector Processor Architectures App 20210216318 - Langhammer; Martin ; et al.	2021-07-15
Continuous carry-chain packing Grant 11,016,733 - Langhammer , et al. May 25, 2	2021-05-25
Reduction operation mapping systems and methods Grant 11,003,446 - Langhammer , et al. May 11, 2	2021-05-11
High Performance Regularized Network-on-Chip Architecture App 20210117607 - Baeckler; Gregg William ; et al.	2021-04-22
High performance regularized network-on-chip architecture Grant 10,922,471 - Baeckler , et al. February 16, 2	2021-02-16
Methods for using a multiplier to support multiple sub-multiplication operations Grant 10,871,946 - Langhammer , et al. December 22, 2	2020-12-22
Method and apparatus for implementing an application aware system on a programmable logic device Grant 10,867,090 - Baeckler , et al. December 15, 2	2020-12-15
Logic circuits with simultaneous dual function capability Grant 10,790,829 - Langhammer , et al. September 29, 2	2020-09-29
Programmable Integrated Circuit Underlay App 20200293707 - Baeckler; Gregg William ; et al.	2020-09-17
Hazard Mitigation for Lightweight Processor Cores App 20200278865 - Langhammer; Martin ; et al.	2020-09-03
Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension Grant 10,732,932 - Pasca , et al.	2020-08-04
Programmable Logic Device With Fine-grained Disaggregation App 20200186149 - Subbareddy; Dheeraj ; et al.	2020-06-11
Methods For Using A Multiplier Circuit To Support Multiple Sub-multiplications Using Bit Correction And Extension App 20200142671 - Pasca; Bogdan ; et al.	2020-05-07
Deterministic Clustering And Packing Method For Random Logic On Programmable Integrated Circuits App 20200125780 - Baeckler; Gregg William ; et al.	2020-04-23
Logic Circuits With Simultaneous Dual Function Capability App 20200106442 - Langhammer; Martin ; et al.	2020-04-02
Programmable logic device with fine-grained disaggregation Grant 10,601,426 - Subbareddy , et al.	2020-03-24
Programmable Logic Device With Fine-grained Disaggregation App 20200083890 - Subbareddy; Dheeraj ; et al.	2020-03-12
Machine Learning Training Architecture For Programmable Devices App 20200026494 - Langhammer; Martin ; et al.	2020-01-23
Geometric Synthesis App 20190324724 - Gribok; Sergey Vladimirovich ; et al.	2019-10-24
High Performance Regularized Network-on-Chip Architecture App 20190318058 - Baeckler; Gregg William ; et al.	2019-10-17
Method And Apparatus For Implementing An Application Aware System On A Programmable Logic Device App 20190213289 - BAECKLER; Gregg William ; et al.	2019-07-11
Scalable circuitry and method for control insertion Grant 10,296,479 - Baeckler , et al.	2019-05-21
Method And Apparatus For Performing Multiplier Regularization App 20190121927 - LANGHAMMER; Martin ; et al.	2019-04-25
Method And Apparatus For Performing Synthesis For Field Programmable Gate Array Embedded Feature Placement App 20190042683 - LANGHAMMER; Martin ; et al.	2019-02-07
Continuous Carry-Chain Packing App 20190042200 - Langhammer; Martin ; et al.	2019-02-07
Circuitry For Low-precision Deep Learning App 20190042939 - Langhammer; Martin ; et al.	2019-02-07
Programmable-Logic-Directed Multiplier Mapping App 20190042197 - Langhammer; Martin ; et al.	2019-02-07
Method And Apparatus For Performing Field Programmable Gate Array Packing With Continuous Carry Chains App 20190042674 - Langhammer; Martin ; et al.	2019-02-07
Methods For Using A Multiplier To Support Multiple Sub-multiplication Operations App 20190042198 - Langhammer; Martin ; et al.	2019-02-07
Reduction Operation Mapping Systems And Methods App 20190018673 - Langhammer; Martin ; et al.	2019-01-17
Method and apparatus for improving a design for a system during compilation by performing network replacement Grant 10,162,919 - Baeckler Dec	2018-12-25
Move based XOR optimization Grant 10,073,940 - Baeckler September 11, 2	2018-09-11
Distributed burst error protection Grant 9,941,903 - Mendel , et al. April 10, 2	2018-04-10
Apparatus for improved communication and associated methods Grant 9,544,092 - Baeckler , et al. January 10, 2	2017-01-10
Central alignment circutry for high-speed serial receiver circuits Grant 9,461,837 - Baeckler October 4, 2	2016-10-04
Preemptively generating statistical feedback on a design file and presenting the feedback in an input context Grant 9,417,984 - Drury , et al. August 16, 2	2016-08-16
Apparatus and methods for tuning a communication link for power conservation Grant 9,419,746 - Baeckler , et al. August 16, 2	2016-08-16
First-in first-out circuits and methods Grant 9,330,740 - Baeckler , et al. May 3, 2	2016-05-03
Hierarchical cyclic redundancy check circuitry Grant 9,312,883 - Mendel , et al. April 12, 2	2016-04-12
Network interface circuitry with flexible memory addressing capabilities Grant 9,304,899 - Baeckler April 5, 2	2016-04-05
Methods and apparatus for detecting and correcting errors in high-speed serial communications systems Grant 9,274,880 - Mendel , et al. March 1, 2	2016-03-01
Method and apparatus for analyzing structured cell candidates for structured application specific integrated circuits Grant 9,251,305 - Baeckler February 2, 2	2016-02-02
Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement Grant 9,230,047 - Van Antwerpen , et al. January 5, 2	2016-01-05
Methods and apparatus for performing bit swapping in clock data recovery circuitry Grant 9,203,604 - Mendel , et al. December 1, 2	2015-12-01
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 9,172,378 - Hutton , et al. October 27, 2	2015-10-27
Method and system for dynamic table line encoding Grant 9,100,031 - Baeckler , et al. August 4, 2	2015-08-04
Register retiming technique Grant 9,053,274 - van Antwerpen , et al. June 9, 2	2015-06-09
High-speed data communications architecture Grant 9,048,889 - Vijayaraghavan , et al. June 2, 2	2015-06-02
Method and apparatus for performing parallel synthesis on a field programmable gate array Grant 8,954,906 - Baeckler , et al. February 10, 2	2015-02-10
Distributed burst error protection Grant 8,943,393 - Mendel , et al. January 27, 2	2015-01-27
Central Alignment Circutry For High-speed Serial Receiver Circuits App 20150003477 - Baeckler; Gregg William	2015-01-01
Methods for testing network circuitry Grant 8,918,682 - Baeckler December 23, 2	2014-12-23
Apparatus For Improved Communication And Associated Methods App 20140269983 - Baeckler; Gregg William ; et al.	2014-09-18
Signal flow control through clock signal rate adjustments Grant 8,810,299 - Baeckler , et al. August 19, 2	2014-08-19
Register retiming technique Grant 8,806,399 - van Antwerpen , et al. August 12, 2	2014-08-12
Lane specific CRC Grant 8,775,894 - Mendel , et al. July 8, 2	2014-07-08
Method and apparatus for extracted synthesis gate characteristics model Grant 8,756,540 - Baeckler , et al. June 17, 2	2014-06-17
Methods for Testing Network Circuitry App 20140136905 - Baeckler; Gregg William	2014-05-15
Signal Flow Control Through Clock Signal Rate Adjustments App 20140097877 - Baeckler; Gregg William ; et al.	2014-04-10
Method and apparatus for performing parallel synthesis on a field programmable gate array Grant 8,661,380 - Baeckler , et al. February 25, 2	2014-02-25
Method and system for dynamic table line encoding Grant 8,638,245 - Baeckler , et al. January 28, 2	2014-01-28
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 8,601,424 - Hutton , et al. December 3, 2	2013-12-03
Signature based duplicate extraction Grant 8,479,143 - Baeckler July 2, 2	2013-07-02
Methods and apparatus for error checking code decomposition Grant 8,429,491 - Baeckler , et al. April 23, 2	2013-04-23
Low latency floating-point divider Grant 8,176,111 - Liu , et al. May 8, 2	2012-05-08
Early logic mapper during FPGA synthesis Grant 8,166,436 - Baeckler April 24, 2	2012-04-24
Heterogeneous labs Grant 7,902,864 - Hutton , et al. March 8, 2	2011-03-08
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,890,910 - Hutton , et al. February 15, 2	2011-02-15
Method and apparatus for deriving signal activities for power analysis and optimization Grant 7,877,710 - Neto , et al. January 25, 2	2011-01-25
Hardware acceleration of functional factoring Grant 7,797,667 - Baeckler September 14, 2	2010-09-14
SAT-based technology mapping framework Grant 7,725,871 - Safarpour , et al. May 25, 2	2010-05-25
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,705,628 - Hutton , et al. April 27, 2	2010-04-27
Hardware acceleration of functional factoring Grant 7,640,528 - Baeckler December 29, 2	2009-12-29
Methods and apparatus for error checking code decomposition Grant 7,634,705 - Baeckler , et al. December 15, 2	2009-12-15
Method for early logic mapping during FPGA synthesis Grant 7,543,265 - Baeckler June 2, 2	2009-06-02
State machine recognition and optimization Grant 7,441,212 - van Antwerpen , et al. October 21, 2	2008-10-21
Method and apparatus for reducing synthesis runtime Grant 7,415,693 - van Antwerpen , et al. August 19, 2	2008-08-19
SAT-based technology mapping framework Grant 7,386,828 - Safarpour , et al. June 10, 2	2008-06-10
Methods of producing application-specific integrated circuit equivalents of programmable logic Grant 7,373,631 - Yuan , et al. May 13, 2	2008-05-13
Technology mapping techniques for incomplete lookup tables Grant 7,249,329 - Baeckler , et al. July 24, 2	2007-07-24
Fast method for functional mapping to incomplete LUT pairs Grant 7,224,183 - Baeckler , et al. May 29, 2	2007-05-29
Fast method for functional mapping to incomplete LUT pairs App 20070035327 - Baeckler; Gregg William ; et al.	2007-02-15