Baeckler; Gregg
Patent Applications and Registrations
Patent applications and USPTO patent grants for Baeckler; Gregg.The latest application filed is for "logic circuits with augmented arithmetic densities".
- Baeckler; Gregg - San Francisco CA
- Baeckler; Gregg - San Jose CA
| Patent | Date |
|---|---|
| High radix subset code multiplier architecture Grant 11,010,134 - Langhammer , et al. May 18, 2 | 2021-05-18 |
| Logic circuits with augmented arithmetic densities Grant 10,715,144 - Gribok , et al. | 2020-07-14 |
| Logic Circuits With Augmented Arithmetic Densities App 20190288688 - Gribok; Sergey ; et al. | 2019-09-19 |
| Omnibus logic element Grant 10,177,766 - Schleicher , et al. J | 2019-01-08 |
| High Radix Subset Code Multiplier Architecture App 20180364981 - Langhammer; Martin ; et al. | 2018-12-20 |
| Omnibus logic element Grant 9,496,875 - Schleicher , et al. November 15, 2 | 2016-11-15 |
| Omnibus logic element Grant 8,878,567 - Schleicher , et al. November 4, 2 | 2014-11-04 |
| Omnibus logic element for packing or fracturing Grant 8,593,174 - Schleicher , et al. November 26, 2 | 2013-11-26 |
| Register retiming technique Grant 8,402,408 - van Antwerpen , et al. March 19, 2 | 2013-03-19 |
| Omnibus logic element for packing or fracturing Grant 8,237,465 - Schleicher , et al. August 7, 2 | 2012-08-07 |
| Register retiming technique Grant 8,108,812 - van Antwerpen , et al. January 31, 2 | 2012-01-31 |
| Omnibus logic element for packing or fracturing Grant 7,911,230 - Schleicher , et al. March 22, 2 | 2011-03-22 |
| Register retiming technique Grant 7,689,955 - van Antwerpen , et al. March 30, 2 | 2010-03-30 |
| Omnibus logic element Grant 7,671,625 - Schleicher , et al. March 2, 2 | 2010-03-02 |
| Extracting synchronous secondary signals by functional analysis Grant 7,636,655 - Baeckler December 22, 2 | 2009-12-22 |
| Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,594,208 - Borer , et al. September 22, 2 | 2009-09-22 |
| Logic cell supporting addition of three binary words Grant 7,565,388 - Baeckler , et al. July 21, 2 | 2009-07-21 |
| Omnibus logic element Grant 7,538,579 - Schleicher , et al. May 26, 2 | 2009-05-26 |
| Techniques for mapping to a shared lookup table mask Grant 7,350,176 - Baeckler , et al. March 25, 2 | 2008-03-25 |
| Physical resynthesis of a logic design Grant 7,337,100 - Hutton , et al. February 26, 2 | 2008-02-26 |
| Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,181,703 - Borer , et al. February 20, 2 | 2007-02-20 |
| Omnibus logic element including look up table based logic elements Grant 7,167,022 - Schleicher , et al. January 23, 2 | 2007-01-23 |
| Register retiming technique Grant 7,120,883 - van Antwerpen , et al. October 10, 2 | 2006-10-10 |
| Verifying logic synthesizers Grant 7,080,333 - Ratchev , et al. July 18, 2 | 2006-07-18 |
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