Babayan; Boris A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Babayan; Boris A..The latest application filed is for "method and apparatus to create register windows for parallel iterations to achieve high performance in hw-sw codesigned loop accelerator".

Company Profile

0.15.21

Babayan; Boris A. - Moscow RU
BABAYAN; BORIS A. - Kiryat Tivon IL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instructions for manipulating a multi-bit predicate register for predicating instruction sequences Grant 10,579,378 - Grochowski , et al.	2020-03-03
Instruction and logic for sorting and retiring stores Grant 10,514,927 - Lechanka , et al. Dec	2019-12-24
Apparatus and methods to support counted loop exits in a multi-strand loop processor Grant 10,241,794 - Scherbinin , et al.	2019-03-26
Method to do control speculation on loads in a high performance strand-based loop accelerator Grant 10,241,789 - Ostanevich , et al.	2019-03-26
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator Grant 10,241,801 - Iyer , et al.	2019-03-26
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor Grant 10,235,171 - Ostanevich , et al.	2019-03-19
Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor Grant 10,133,582 - Kosarev , et al. November 20, 2	2018-11-20
Hardware apparatuses and methods to control access to a multiple bank data cache Grant 10,095,623 - Kluchnikov , et al. October 9, 2	2018-10-09
Method And Apparatus To Efficiently Handle Allocation Of Memory Ordering Buffers In A Multi-strand Out-of-order Loop Processor App 20180181397 - OSTANEVICH; Alexander Y. ; et al.	2018-06-28
Method And Apparatus To Create Register Windows For Parallel Iterations To Achieve High Performance In Hw-sw Codesigned Loop Accelerator App 20180181405 - IYER; Jayesh ; et al.	2018-06-28
Apparatus And Methods Of Decomposing Loops To Improve Performance And Power Efficiency App 20180181398 - Scherbinin; Sergey P. ; et al.	2018-06-28
Method To Do Control Speculation On Loads In A High Performance Strand-based Loop Accelerator App 20180181396 - OSTANEVICH; Alexander Y. ; et al.	2018-06-28
Apparatus And Methods To Support Counted Loop Exits In A Multi-strand Loop Processor App 20180181400 - Scherbinin; Sergey P. ; et al.	2018-06-28
Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor Grant 9,811,340 - Kosarev , et al. November 7, 2	2017-11-07
Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order Processor App 20170235578 - Babayan; Boris A. ; et al.	2017-08-17
Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor Grant 9,645,819 - Iyer , et al. May 9, 2	2017-05-09
Hardware-assisted Software Verification And Secure Execution App 20170090929 - Muttik; Igor ; et al.	2017-03-30
Hardware Apparatuses And Methods To Control Access To A Multiple Bank Data Cache App 20170039139 - KLUCHNIKOV; ANDREY ; et al.	2017-02-09
Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits Grant 9,529,596 - Babayan , et al. December 27, 2	2016-12-27
Instruction and Logic for Sorting and Retiring Stores App 20160364239 - Lechenko; Anton ; et al.	2016-12-15
Processor Logic And Method For Dispatching Instructions From Multiple Strands App 20160364237 - Kosarev; Nikolay ; et al.	2016-12-15
Instruction And Logic For Identifying Instructions For Retirement In A Multi-strand Out-of-order Processor App 20160314000 - Kosarev; Nikolay ; et al.	2016-10-27
Instruction And Logic For Memory Access In A Clustered Wide-execution Machine App 20160306742 - LECHENKO; Anton W. ; et al.	2016-10-20
Hardware apparatuses and methods to control access to a multiple bank data cache Grant 9,471,501 - Kluchnikov , et al. October 18, 2	2016-10-18
Hardware Apparatuses And Methods To Control Access To A Multiple Bank Data Cache App 20160092367 - Kluchnikov; Andrey ; et al.	2016-03-31
Method And Apparatus For Non-speculative Fetch And Execution Of Control-dependent Blocks App 20160055004 - GROCHOWSKI; EDWARD T. ; et al.	2016-02-25
Method And Apparatus For Executing Instructions Using A Predicate Register App 20150277910 - GROCHOWSKI; EDWARD T. ; et al.	2015-10-01
Instruction Scheduling For A Multi-strand Out-of-order Processor App 20140208074 - Babayan; Boris A. ; et al.	2014-07-24
Method And Apparatus For Reducing Area And Complexity Of Instruction Wakeup Logic In A Multi-strand Out-of-order Processor App 20130339679 - IYER; Jayesh ; et al.	2013-12-19
Method And Apparatus For Scheduling Of Instructions In A Multi-strand Out-of-order Processor App 20130007415 - Babayan; Boris A. ; et al.	2013-01-03

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