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Patent applications and USPTO patent grants for Azim; Syed K..The latest application filed is for "testing of high speed ddr interface using single clock edge triggered tester data".
Patent | Date |
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System and method for synchronizing a selected master circuit with a slave circuit by receiving and forwarding a control signal between the circuits and operating the circuits based on their received control signal Grant 6,952,789 - Azim , et al. October 4, 2 | 2005-10-04 |
Testing of high speed DDR interface using single clock edge triggered tester data Grant 6,691,272 - Azim February 10, 2 | 2004-02-10 |
Testing of high speed DDR interface using single clock edge triggered tester data App 20020071334 - Azim, Syed K. | 2002-06-13 |
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