Azema; Jerome Laurent

Patent Applications and Registrations

Patent applications and USPTO patent grants for Azema; Jerome Laurent.The latest application filed is for "method and system of verifying proper execution of a secure mode entry sequence".

Company Profile

0.7.9

Azema; Jerome Laurent - Villeneuve-Loubet FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method And System Of Verifying Proper Execution Of A Secure Mode Entry Sequence App 20210141871 - Conti; Gregory Remy Philippe ; et al.	2021-05-13
Monitoring circuit for allowing a processor to enter secure mode upon confirming proper execution of a non-speculative instruction Grant 10,902,092 - Conti , et al. January 26, 2	2021-01-26
Method And System Of Verifying Proper Execution Of A Secure Mode Entry Sequence App 20150178513 - Conti; Gregory Remy Philippe ; et al.	2015-06-25
System and method for secure mode for processors and memories on multiple semiconductor dies within a single semiconductor package Grant 9,063,889 - Conti , et al. June 23, 2	2015-06-23
State machine for monitoring a trace port and verifying proper execution of a secure mode entry sequence instruction Grant 8,966,226 - Conti , et al. February 24, 2	2015-02-24
Secure Time/Date Virtualization App 20120278880 - Leterrier; Guillaume ; et al.	2012-11-01
System and method of identifying and preventing security violations within a computing system Grant 8,220,045 - Conti , et al. July 10, 2	2012-07-10
Secure time/date virtualization Grant 8,220,031 - Leterrier , et al. July 10, 2	2012-07-10
Secure Time/date Virtualization App 20080276298 - Leterrier; Guillaume ; et al.	2008-11-06
Method and system for detecting a security violation using an error correction code App 20060080580 - Conti; Gregory Remy Philippe ; et al.	2006-04-13
System and method of identifying and preventing security violations within a computing system App 20060021035 - Conti; Gregory Remy Philippe ; et al.	2006-01-26
System and method for secure mode for processors and memories on multiple semiconductor dies within a single semiconductor package App 20060015947 - Conti; Gregory Remy Philippe ; et al.	2006-01-19
Method and system of ensuring integrity of a secure mode entry sequence App 20060004964 - Conti; Gregory Remy Philippe ; et al.	2006-01-05
Method and system of verifying proper execution of a secure mode entry sequence App 20060005072 - Philippe Conti; Gregory Remy ; et al.	2006-01-05

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