Avanzino; Steven C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Avanzino; Steven C..The latest application filed is for "protection of low-k ild during damascene processing with thin liner".

Company Profile

0.65.10

Avanzino; Steven C. - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Ordered porosity to direct memory element formation Grant 7,776,682 - Nickel , et al. August 17, 2	2010-08-17
Solutions for controlled, selective etching of copper Grant 7,465,408 - Avanzino December 16, 2	2008-12-16
Memory cell and method of making the memory cell Grant 7,306,988 - Avanzino , et al. December 11, 2	2007-12-11
Use of Ta-capped metal line to improve formation of memory element films Grant 7,288,782 - Avanzino , et al. October 30, 2	2007-10-30
Semiconductor device with electrically biased die edge seal Grant 7,235,867 - Augur , et al. June 26, 2	2007-06-26
Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures Grant 7,232,765 - Avanzino , et al. June 19, 2	2007-06-19
Composite tantalum nitride/tantalum copper capping layer Grant 7,157,795 - Erb , et al. January 2, 2	2007-01-02
Method of forming copper sulfide layer over substrate Grant 7,148,144 - Avanzino December 12, 2	2006-12-12
Method of making a memory cell Grant 7,141,482 - Avanzino November 28, 2	2006-11-28
Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film Grant 7,129,133 - Avanzino , et al. October 31, 2	2006-10-31
Use of Ta-capped metal line to improve formation of memory element films Grant 7,084,062 - Avanzino , et al. August 1, 2	2006-08-01
Metal bridging monitor for etch and CMP endpoint detection Grant 7,011,762 - Lyons , et al. March 14, 2	2006-03-14
Conformal barrier liner in an integrated circuit interconnect Grant 6,989,604 - Woo , et al. January 24, 2	2006-01-24
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers Grant 6,979,903 - Avanzino , et al. December 27, 2	2005-12-27
Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process Grant 6,934,032 - Subramanian , et al. August 23, 2	2005-08-23
Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap Grant 6,841,473 - Wang , et al. January 11, 2	2005-01-11
Protection of low-k ILD during damascene processing with thin liner Grant 6,836,017 - Ngo , et al. December 28, 2	2004-12-28
Model based metal overetch control Grant 6,808,591 - Phan , et al. October 26, 2	2004-10-26
Scatterometry of grating structures to monitor wafer stress Grant 6,771,356 - Lyons , et al. August 3, 2	2004-08-03
Protection of low-k ILD during damascene processing with thin liner App 20040147117 - Ngo, Minh Van ; et al.	2004-07-29
Low temperature dielectric deposition to improve copper electromigration performance Grant 6,756,306 - Avanzino , et al. June 29, 2	2004-06-29
Protection low-k ILD during damascene processing with thin liner Grant 6,723,635 - Ngo , et al. April 20, 2	2004-04-20
Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties Grant 6,720,264 - Sahota , et al. April 13, 2	2004-04-13
Use of scatterometry/reflectometry to measure thin film delamination during CMP Grant 6,702,648 - Avanzino , et al. March 9, 2	2004-03-09
Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects Grant 6,699,785 - Yang , et al. March 2, 2	2004-03-02
Low temperature dielectric deposition to improve copper electromigration performance App 20040023511 - Avanzino, Steven C. ; et al.	2004-02-05
Sensor to predict void free films using various grating structures and characterize fill performance Grant 6,684,172 - Subramanian , et al. January 27, 2	2004-01-27
Integrated circuit having increased gate coupling capacitance Grant 6,682,978 - Park , et al. January 27, 2	2004-01-27
Integrated circuit with low solubility metal-conductor interconnect cap Grant 6,657,303 - Wang , et al. December 2, 2	2003-12-02
Conformal barrier liner in an integrated circuit interconnect Grant 6,657,304 - Woo , et al. December 2, 2	2003-12-02
Process for formation of a wiring network using a porous interlevel dielectric and related structures App 20030218253 - Avanzino, Steven C. ; et al.	2003-11-27
Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers Grant 6,642,145 - Avanzino , et al. November 4, 2	2003-11-04
Integrated pressure sensor for measuring multiaxis pressure gradients App 20030188829 - Rangarajan, Bharath ; et al.	2003-10-09
Metal bridging monitor for etch and CMP endpoint detection Grant 6,624,642 - Lyons , et al. September 23, 2	2003-09-23
Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects App 20030146512 - Yang, Kai ; et al.	2003-08-07
Methods of forming capped copper interconnects with improved electromigration resistance Grant 6,599,827 - Ngo , et al. July 29, 2	2003-07-29
Chemically preventing Cu dendrite formation and growth by immersion Grant 6,596,637 - Schonauer , et al. July 22, 2	2003-07-22
Interconnect methodology employing a low dielectric constant etch stop layer Grant 6,593,632 - Avanzino , et al. July 15, 2	2003-07-15
Wafer based temperature sensors for characterizing chemical mechanical polishing processes Grant 6,562,185 - Avanzino , et al. May 13, 2	2003-05-13
Wafer Based Temperature Sensors For Characterizing Chemical Mechanical Polishing Processes App 20030055526 - Avanzino, Steven C. ; et al.	2003-03-20
Interconnect structure formed in porous dielectric material with minimized degradation and electromigration Grant 6,528,409 - Lopatin , et al. March 4, 2	2003-03-04
Graded low-k middle-etch stop layer for dual-inlaid patterning Grant 6,525,428 - Ngo , et al. February 25, 2	2003-02-25
Ta barrier slurry containing an organic additive Grant 6,503,418 - Sahota , et al. January 7, 2	2003-01-07
Anneal hillock suppression method in integrated circuit interconnects Grant 6,500,754 - Erb , et al. December 31, 2	2002-12-31
Method of copper-polysilicon T-gate formation Grant 6,500,743 - Lopatin , et al. December 31, 2	2002-12-31
Conductor chemical-mechanical polishing in integrated circuit interconnects App 20020173140 - Sahota, Kashmir S. ; et al.	2002-11-21
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers Grant 6,469,385 - Avanzino , et al. October 22, 2	2002-10-22
Tantalum anodization for in-laid copper metallization capacitor Grant 6,433,379 - Lopatin , et al. August 13, 2	2002-08-13
Method of improving electromigration resistance of capped Cu Grant 6,432,822 - Ngo , et al. August 13, 2	2002-08-13
Dielectric protected chemical-mechanical polishing in integrated circuit interconnects Grant 6,413,869 - Achuthan , et al. July 2, 2	2002-07-02
Controlled Anneal Conductors For Integrated Circuit Interconnects App 20020076923 - Avanzino, Steven C. ; et al.	2002-06-20
Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation App 20020072219 - Avanzino, Steven C. ; et al.	2002-06-13
Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film Grant 6,350,687 - Avanzino , et al. February 26, 2	2002-02-26
Ta Barrier Slurry Containing An Organic Additive App 20020005504 - SAHOTA, KASHMIR S. ; et al.	2002-01-17
Ceria removal in chemical-mechanical polishing of integrated circuits Grant 6,326,305 - Avanzino , et al. December 4, 2	2001-12-04
Chemically preventing copper dendrite formation and growth by spraying Grant 6,319,833 - Schonauer , et al. November 20, 2	2001-11-20
Method and apparatus for improved planarity metallization by electroplating and CMP Grant 6,319,834 - Erb , et al. November 20, 2	2001-11-20
Low-k photoresist removal process Grant 6,235,453 - You , et al. May 22, 2	2001-05-22
Optimized trench/via profile for damascene filling Grant 6,211,071 - Lukanc , et al. April 3, 2	2001-04-03
Chemically preventing Cu dendrite formation and growth by double sided scrubbing Grant 6,197,690 - Schonauer , et al. March 6, 2	2001-03-06
Method for multiple phase polishing of a conductive layer in a semidonductor wafer Grant 6,184,141 - Avanzino , et al. February 6, 2	2001-02-06
Chemically removable Cu CMP slurry abrasive Grant 6,169,034 - Avanzino , et al. January 2, 2	2001-01-02
Chemically removable Cu CMP slurry abrasive Grant 6,140,239 - Avanzino , et al. October 31, 2	2000-10-31
Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Grant 6,137,126 - Avanzino , et al. October 24, 2	2000-10-24
Sputter-resistant hardmask for damascene trench/via formation Grant 6,121,150 - Avanzino , et al. September 19, 2	2000-09-19
Optimized trench/via profile for damascene filling Grant 6,121,149 - Lukanc , et al. September 19, 2	2000-09-19
Optimized trench/via profile for damascene processing Grant 6,117,781 - Lukanc , et al. September 12, 2	2000-09-12
Optimized trench/via profile for damascene filling Grant 6,117,782 - Lukanc , et al. September 12, 2	2000-09-12
Method of preventing copper dendrite formation and growth Grant 6,074,949 - Schonauer , et al. June 13, 2	2000-06-13
Methodology for developing product-specific interlayer dielectric polish processes Grant 5,665,199 - Sahota , et al. September 9, 1	1997-09-09
Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning Grant 5,662,769 - Schonauer , et al. September 2, 1	1997-09-02
Void free oxide fill for interconnect spaces Grant 5,382,547 - Sultan , et al. January 17, 1	1995-01-17
Dopant sources for CMOS device Grant 5,116,778 - Haskell , et al. May 26, 1	1992-05-26
Method of planarization of topologies in integrated circuit structures Grant 4,962,064 - Haskell , et al. October 9, 1	1990-10-09
Method of planarization of topologies in integrated circuit structures Grant 4,954,459 - Avanzino , et al. September 4, 1	1990-09-04

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