auvinen stuart t

Patent Applications and Registrations

Patent applications and USPTO patent grants for auvinen stuart t.The latest application filed is for "ram based fifo memory half-full detection apparatus and method".

Company Profile

17.4.0

- unknown
Auvinen; Stuart T. - Santa Cruz CA
Auvinen; Stuart T. - Capitola CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Seamless switching of resonant tanks in power converters by matching voltage gains at tank switchover Grant 10938310 -	2021-03-02
Method and system for integrated circuit (IC) layout migration integrated with layout expertise Grant 10885256 -	2021-01-05
Advanced multi-gain calibration for direct modulation synthesizer Grant 10862427 -	2020-12-08
Dynamic multi-view rendering for autostereoscopic displays by generating reduced number of views for less-critical segments based on saliency/depth/eye gaze map Grant 10855965 -	2020-12-01
Digital shunt regulation for a wireless-power receiver Grant 10848005 -	2020-11-24
Modified pseudo-cylindrical mapping of spherical video using linear interpolation of empty areas for compression of streamed images Grant 10735765 -	2020-08-04
Adaptive non-linearity identification and compensation using orthogonal functions in a mixed signal circuit Grant 10707883 -	2020-07-07
Low capacitance and high-holding-voltage transient-voltage-suppressor (TVS) device for electro-static-discharge (ESD) protection Grant 10665584 -	2020-05-26
Step fin field-effect-transistor (FinFET) with slim top of fin and thick bottom of fin for electro-static-discharge (ESD) or electrical over-stress (EOS) protection Grant 10510743 -	2019-12-17
Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells Grant 10504886 -	2019-12-10
Calibration of radix errors using Least-Significant-Bit (LSB) averaging in a Successive-Approximation Register Analog-Digital Converter (SAR-ADC) during a fully self-calibrating routine Grant 10483995 -	2019-11-19
50% duty cycle quadrature-in and quadrature-out (QIQO) divide-by-3 circuit Grant 10454462 -	2019-10-22
Power supply switch with programmable switching decision Grant 10452113 -	2019-10-22
Duty cycle controller with calibration circuit Grant 10418978 -	2019-09-17
RC oscillator that uses thermometer codes to select a sub-array and binary codes to select capacitors or resistors within a sub-array for linear and monotonic tuning Grant 10305425 -	2019-05-28
Current-sharing circuit for DC-DC converters Grant 10211728 -	2019-02-19
Clock duty cycle calibration and frequency multiplier circuit Grant 10181844 -	2019-01-15
RAM based FIFO memory half-full detection apparatus and method Grant 5,490,257 - Hoberman , et al. February 6, 1	1996-02-06
Data cache management system with test mode using index registers and CAS disable and posted write disable Grant 5,276,833 - Auvinen , et al. January 4, 1	1994-01-04
Interleaved sensing system for FIFO and burst-mode memories Grant 4,954,987 - Auvinen , et al. September 4, 1	1990-09-04
Fast flush for a first-in first-out memory Grant 4,802,122 - Auvinen , et al. January 31, 1	1989-01-31

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