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Patent applications and USPTO patent grants for Austemper Design Systems Inc..The latest application filed is for "systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device".
Patent | Date |
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Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation Grant 10,522,237 - Pillay Dec | 2019-12-31 |
Systems And Methods For Analyzing Failure Rates Due To Soft/hard Errors In The Design Of A Digital Electronic Device App 20180364306 - Pillay; Sanjay ;   et al. | 2018-12-20 |
Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof Grant 9,991,008 - Pillay June 5, 2 | 2018-06-05 |
Low Power Vlsi Designs Using Circuit Failure In Sequential Cells As Low Voltage Check For Limit Of Operation App 20170212972 - Pillay; Sanjay | 2017-07-27 |
Systems And Methods For Analyzing Soft Errors In A Design And Reducing The Associated Failure Rates Thereof App 20170213602 - Pillay; Sanjay | 2017-07-27 |
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