| Patent | Date |
|---|
Power efficient instruction prefetch mechanism
Grant 8,661,229 - Sartorius , et al. February 25, 2 | 2014-02-25 |
Cache locking without interference from normal allocations
Grant 8,527,713 - Augsburg , et al. September 3, 2 | 2013-09-03 |
Address translation method and apparatus
Grant 8,239,657 - Kopec , et al. August 7, 2 | 2012-08-07 |
Latency insensitive FIFO signaling protocol
Grant 7,725,625 - Dockser , et al. May 25, 2 | 2010-05-25 |
Translation lookaside buffer manipulation
Grant 7,721,067 - Kopec , et al. May 18, 2 | 2010-05-18 |
Method and apparatus for managing cache partitioning using a dynamic boundary
Grant 7,650,466 - Stempel , et al. January 19, 2 | 2010-01-19 |
Power efficient instruction prefetch mechanism
Grant 7,587,580 - Sartorius , et al. September 8, 2 | 2009-09-08 |
Power Efficient Instruction Prefetch Mechanism
App 20090210663 - Sartorius; Thomas Andrew ; et al. | 2009-08-20 |
Latency insensitive FIFO signaling protocol
Grant 7,454,538 - Dockser , et al. November 18, 2 | 2008-11-18 |
Latency Insensitive FIFO Signaling Protocol
App 20080281996 - Dockser; Kenneth Alan ; et al. | 2008-11-13 |
Methods and apparatus for predicting unaligned memory access
Grant 7,437,537 - Bridges , et al. October 14, 2 | 2008-10-14 |
TLB lock indicator
Grant 7,426,626 - Augsburg , et al. September 16, 2 | 2008-09-16 |
Speculative Instruction Issue in a Simultaneously Multithreaded Processor
App 20080189521 - Augsburg; Victor Roberts ; et al. | 2008-08-07 |
Address Translation Method and Apparatus
App 20080189506 - Kopec; Brian Joseph ; et al. | 2008-08-07 |
Method and system for optimizing translation lookaside buffer entries
Grant 7,366,869 - Sartorius , et al. April 29, 2 | 2008-04-29 |
Speculative instruction issue in a simultaneously multithreaded processor
Grant 7,366,877 - Augsburg , et al. April 29, 2 | 2008-04-29 |
Global modified indicator to reduce power consumption on cache miss
Grant 7,330,941 - Sartorius , et al. February 12, 2 | 2008-02-12 |
System on a chip bus with automatic pipeline stage insertion for timing closure
Grant 7,296,175 - Augsburg , et al. November 13, 2 | 2007-11-13 |
Cache locking without interference from normal allocations
App 20070180199 - Augsburg; Victor Roberts ; et al. | 2007-08-02 |
Translation lookaside buffer manipulation
App 20070174584 - Kopec; Brian Joseph ; et al. | 2007-07-26 |
Updating multiple levels of translation lookaside buffers (TLBs) field
App 20070094476 - Augsburg; Victor Roberts ; et al. | 2007-04-26 |
Method and apparatus for managing cache partitioning
App 20070067574 - Stempel; Brian Michael ; et al. | 2007-03-22 |
TLB lock indicator
App 20070050594 - Augsburg; Victor Roberts ; et al. | 2007-03-01 |
Preventing multiple translation lookaside buffer accesses for a same page in memory
App 20070005933 - Kopec; Brian Joseph ; et al. | 2007-01-04 |
Latency insensitive FIFO signaling protocol
App 20060259669 - Dockser; Kenneth Alan ; et al. | 2006-11-16 |
Global modified indicator to reduce power consumption on cache miss
App 20060218354 - Sartorius; Thomas Andrew ; et al. | 2006-09-28 |
Method and system for optimizing translation lookaside buffer entries
App 20060212675 - Sartorius; Thomas Andrew ; et al. | 2006-09-21 |
Unaligned memory access prediction
App 20060184738 - Bridges; Jeffrey Todd ; et al. | 2006-08-17 |
Power efficient instruction prefetch mechanism
App 20060174090 - Sartorius; Thomas Andrew ; et al. | 2006-08-03 |
Fractional-word writable architected register for direct accumulation of misaligned data
App 20060174066 - Bridges; Jeffrey Todd ; et al. | 2006-08-03 |
Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target
Grant 7,035,958 - Augsburg , et al. April 25, 2 | 2006-04-25 |
Efficiently calculating a branch target address
Grant 6,948,053 - Augsburg , et al. September 20, 2 | 2005-09-20 |
Method for moving snoop pushes to the front of a request queue
Grant 6,907,502 - Augsburg , et al. June 14, 2 | 2005-06-14 |
Speculative instruction issue in a simultaneously multithreaded processor
App 20050060518 - Augsburg, Victor Roberts ; et al. | 2005-03-17 |
System on a chip bus with automatic pipeline stage insertion for timing closure
App 20050055655 - Augsburg, Victor Roberts ; et al. | 2005-03-10 |
System on a chip bus with automatic pipeline stage insertion for timing closure
Grant 6,834,378 - Augsburg , et al. December 21, 2 | 2004-12-21 |
System and method for tracing program instructions before and after a trace triggering event within a processor
Grant 6,826,747 - Augsburg , et al. November 30, 2 | 2004-11-30 |
Reducing power in a snooping cache based multiprocessor environment
Grant 6,826,656 - Augsburg , et al. November 30, 2 | 2004-11-30 |
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
Grant 6,816,962 - Augsburg , et al. November 9, 2 | 2004-11-09 |
Multiprocessor environment supporting variable-sized coherency transactions
Grant 6,807,608 - Augsburg , et al. October 19, 2 | 2004-10-19 |
Reordering of requests between an initiator and the request queue of a bus controller
App 20040068603 - Augsburg, Victor Roberts ; et al. | 2004-04-08 |
Method for moving snoop pushes to the front of a request queue
App 20040068623 - Augsburg, Victor Roberts ; et al. | 2004-04-08 |
System on a chip bus with automatic pipeline stage insertion for timing closure
App 20040068707 - Augsburg, Victor Roberts ; et al. | 2004-04-08 |
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
App 20030163670 - Augsburg, Victor Roberts ; et al. | 2003-08-28 |
Efficiently calculating a branch target address
App 20030163677 - Augsburg, Victor Roberts ; et al. | 2003-08-28 |
Multiprocessor environment supporting variable-sized coherency transactions
App 20030159005 - Augsburg, Victor Roberts ; et al. | 2003-08-21 |
Reducing power in a snooping cache based multiprocessor environment
App 20030145174 - Augsburg, Victor Roberts ; et al. | 2003-07-31 |
System and method for tracing program execution within a superscalar processor
Grant 6,513,134 - Augsburg , et al. January 28, 2 | 2003-01-28 |
System and method for tracing program execution within a processor before and after a triggering event
Grant 5,996,092 - Augsburg , et al. November 30, 1 | 1999-11-30 |
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