Aubel; Mark D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Aubel; Mark D..The latest application filed is for "boundary latch and logic placement to satisfy timing constraints".

Company Profile

0.8.1

Aubel; Mark D. - Essex Junction VT
Aubel; Mark D. - Essex Jct. VT
Aubel; Mark D. - Woodbury MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Boundary latch and logic placement to satisfy timing constraints Grant 9,098,669 - Alpert , et al. August 4, 2	2015-08-04
Boundary Latch And Logic Placement To Satisfy Timing Constraints App 20150199465 - Alpert; Charles J. ; et al.	2015-07-16
Method and system allowing for semiconductor design rule optimization Grant 8,839,177 - Aubel , et al. September 16, 2	2014-09-16
Method and apparatus for associating selected circuit instances and for performing a group operation thereon Grant 6,910,200 - Aubel , et al. June 21, 2	2005-06-21
Method and apparatus for providing modularity to a behavioral description of a circuit design Grant 6,754,879 - Alferness , et al. June 22, 2	2004-06-22
Method and apparatus for using a placement tool to manipulate cell substitution lists Grant 6,701,289 - Garnett , et al. March 2, 2	2004-03-02
Method and apparatus for selecting components within a circuit design database Grant 6,684,376 - Kerzman , et al. January 27, 2	2004-01-27
Method and apparatus for selectively viewing nets within a database editor tool Grant 6,516,456 - Garnett , et al. February 4, 2	2003-02-04
Method for placing logic functions and cells in a logic design using floor planning by analogy Grant 5,696,693 - Aubel , et al. December 9, 1	1997-12-09

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