| Patent | Date |
|---|
Apparatus and methods for synchronizing a plurality of double data rate memory ranks
Grant 11,340,786 - Askar May 24, 2 | 2022-05-24 |
Apparatus And Methods For Synchronizing A Plurality Of Double Data Rate Memory Ranks
App 20220057937 - Askar; Tahsin | 2022-02-24 |
Temperature throttling mechanism for DDR3 memory
Grant 9,122,648 - Askar , et al. September 1, 2 | 2015-09-01 |
Memory diagnostics system and method with hardware-based read/write patterns
Grant 8,607,104 - Cho , et al. December 10, 2 | 2013-12-10 |
Memory Diagnostics System And Method With Hardware-based Read/write Patterns
App 20120159271 - Cho; Hanwoo ; et al. | 2012-06-21 |
Optimal solution to control data channels
Grant 8,006,032 - Askar , et al. August 23, 2 | 2011-08-23 |
Method for training dynamic random access memory (DRAM) controller timing delays
Grant 7,924,637 - Searles , et al. April 12, 2 | 2011-04-12 |
Detection of speculative precharge
Grant 7,761,656 - Madrid , et al. July 20, 2 | 2010-07-20 |
Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays
App 20090244997 - Searles; Shawn ; et al. | 2009-10-01 |
Detection Of Speculative Precharge
App 20090055570 - Madrid; Philip E. ; et al. | 2009-02-26 |
Optimal Solution To Control Data Channels
App 20090055572 - Askar; Tahsin ; et al. | 2009-02-26 |
Temperature Throttling Mechanism For Ddr3 Memory
App 20090052266 - Askar; Tahsin ; et al. | 2009-02-26 |
Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system
Grant 6,996,657 - Chambers , et al. February 7, 2 | 2006-02-07 |
Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system
Grant 6,968,417 - Chambers , et al. November 22, 2 | 2005-11-22 |
Apparatus for reordering graphics responses in a peripheral interface circuit for an I/O node of a computer system
Grant 6,883,045 - Askar , et al. April 19, 2 | 2005-04-19 |
Method and apparatus for reordering packet transactions within a peripheral interface circuit
Grant 6,834,314 - Askar December 21, 2 | 2004-12-21 |
Method and apparatus for initiating partial transactions in a peripheral interface circuit for an I/O node of a computer system
Grant 6,823,405 - Askar November 23, 2 | 2004-11-23 |
Method and apparatus for handling split response transactions within a peripheral interface of an I/O node of a computer system
App 20040172493 - Askar, Tahsin | 2004-09-02 |
Buffer circuit for a peripheral interface circuit in an I/O node of a computer system
Grant 6,760,791 - Askar July 6, 2 | 2004-07-06 |
Buffer circuit for rotating outstanding transactions
Grant 6,760,792 - Askar July 6, 2 | 2004-07-06 |
Peripheral interface circuit for handling graphics responses in an I/O node of a computer system
Grant 6,757,755 - Askar , et al. June 29, 2 | 2004-06-29 |
Peripheral interface circuit for an I/O node of a computer system
Grant 6,725,297 - Askar , et al. April 20, 2 | 2004-04-20 |
Peripheral interface circuit for handling graphics responses in an I/O node of a computer system
App 20030074493 - Askar, Tahsin ; et al. | 2003-04-17 |
Memory incoherent verification methodology
Grant 6,173,243 - Lowe , et al. January 9, 2 | 2001-01-09 |
Verification strategy using external behavior modeling
Grant 6,154,801 - Lowe , et al. November 28, 2 | 2000-11-28 |
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