Ashar; Pranav

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ashar; Pranav.The latest application filed is for "methods and systems for correcting x-pessimism in gate-level simulation or emulation".

Company Profile

1.27.17

Ashar; Pranav - Belle Mead NJ US
Ashar; Pranav - Manalapan NJ
Ashar; Pranav - Princeton NJ
Ashar; Pranav - US
Ashar; Pranav - Belle Meade NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and systems for efficient identification of glitch failures in integrated circuits Grant 10,690,722 - Ashar , et al.	2020-06-23
Methods and systems for correcting X-pessimism in gate-level simulation or emulation Grant 9,965,575 - Ashar , et al. May 8, 2	2018-05-08
Methods and Systems for Correcting X-Pessimism in Gate-Level Simulation or Emulation App 20170083650 - Ashar; Pranav ; et al.	2017-03-23
Software verification using range analysis Grant 8,131,532 - Cadambi , et al. March 6, 2	2012-03-06
Iterative abstraction using SAT-based BMC with proof analysis Grant 7,742,907 - Gupta , et al. June 22, 2	2010-06-22
Efficient approaches for bounded model checking Grant 7,711,525 - Ganai , et al. May 4, 2	2010-05-04
Efficient modeling of embedded memories in bounded memory checking Grant 7,386,818 - Ganai , et al. June 10, 2	2008-06-10
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation Grant 7,383,166 - Ashar , et al. June 3, 2	2008-06-03
String Matching Engine App 20080065639 - Choudhary; Ashwini ; et al.	2008-03-13
String Matching Engine For Arbitrary Length Strings App 20080052644 - Ashar; Pranav ; et al.	2008-02-28
Efficient SAT-based unbounded symbolic model checking Grant 7,305,637 - Ganai , et al. December 4, 2	2007-12-04
Efficient distributed SAT and SAT-based distributed bounded model checking Grant 7,203,917 - Ganai , et al. April 10, 2	2007-04-10
Software Verification Using Range Analysis App 20060282806 - CADAMBI; Srihari ; et al.	2006-12-14
Efficient modeling of embedded memories in bounded memory checking App 20060190864 - Ganai; Malay K. ; et al.	2006-08-24
Content-based information retrieval architecture Grant 7,019,674 - Cadambi , et al. March 28, 2	2006-03-28
Property specific testbench generation framework for circuit design validation by guided simulation Grant 6,975,976 - Casavant , et al. December 13, 2	2005-12-13
Efficient SAT-based unbounded symbolic model checking App 20050240885 - Ganai, Malay K. ; et al.	2005-10-27
Content-based information retrieval architecture App 20050174272 - Cadambi, Srihari ; et al.	2005-08-11
Method for design validation using retiming App 20050149301 - Gupta, Aarti ; et al.	2005-07-07
Method for design validation using retiming Grant 6,874,135 - Gupta , et al. March 29, 2	2005-03-29
Iterative abstraction using SAT-based BMC with proof analysis App 20040230407 - Gupta, Aarti ; et al.	2004-11-18
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage Grant 6,816,825 - Ashar , et al. November 9, 2	2004-11-09
Efficient distributed SAT and SAT-based distributed bounded model checking App 20040210860 - Ganai, Malay ; et al.	2004-10-21
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation App 20040148150 - Ashar, Pranav ; et al.	2004-07-29
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation Grant 6,745,160 - Ashar , et al. June 1, 2	2004-06-01
SAT-based image computation with application in reachability analysis Grant 6,728,665 - Gupta , et al. April 27, 2	2004-04-27
Fast error diagnosis for combinational verification Grant 6,662,323 - Ashar , et al. December 9, 2	2003-12-09
Efficient approaches for bounded model checking App 20030225552 - Ganai, Malay ; et al.	2003-12-04
Partition-based decision heuristics for SAT and image computation using SAT and BDDs Grant 6,651,234 - Gupta , et al. November 18, 2	2003-11-18
Method For Design Validation Using Retiming App 20030182638 - GUPTA, AARTI ; et al.	2003-09-25
Hardware acceleration system for logic simulation App 20030105617 - Cadambi, Srihari ; et al.	2003-06-05
Dynamic detection and removal of inactive clauses in SAT with application in image computation Grant 6,496,961 - Gupta , et al. December 17, 2	2002-12-17
Partition-based decision heuristics for SAT and image computation using SAT and BDDs App 20020178424 - Gupta, Aarti ; et al.	2002-11-28
Method and apparatus for SAT solver architecture with very low synthesis and layout overhead Grant 6,415,430 - Ashar , et al. July 2, 2	2002-07-02
Dynamic detection and removal of inactive clauses in sat with application in image computation App 20020053064 - Gupta, Aarti ; et al.	2002-05-02
Method and apparatus for edge-endpoint-based VLSI design rule checking Grant 6,324,673 - Luo , et al. November 27, 2	2001-11-27
Configurable hardware system implementing Boolean Satisfiability and method thereof Grant 6,247,164 - Ashar , et al. June 12, 2	2001-06-12
Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow Grant 6,163,876 - Ashar , et al. December 19, 2	2000-12-19
Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware Grant 6,038,392 - Ashar , et al. March 14, 2	2000-03-14
Breadth-first manipulation of binary decision diagrams Grant 5,748,486 - Ashar , et al. May 5, 1	1998-05-05
Timing analysis of VLSI circuits Grant 5,457,638 - Ashar , et al. October 10, 1	1995-10-10

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