Arunachalam; Valli

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arunachalam; Valli.The latest application filed is for "integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures".

Company Profile

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Arunachalam; Valli - Pleasant Valley NY
Arunachalam; Valli - Garland TX
Arunachalam, Valli - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures Grant 9,142,633 - Besser , et al. September 22, 2	2015-09-22
Methods for fabricating integrated circuits having low resistance metal gate structures Grant 8,778,789 - Besser , et al. July 15, 2	2014-07-15
Integrated Circuits And Methods For Fabricating Integrated Circuits With Silicide Contacts On Non-planar Structures App 20140167264 - Besser; Paul R. ; et al.	2014-06-19
Methods For Fabricating Integrated Circuits Having Low Resistance Metal Gate Structures App 20140154877 - Besser; Paul R. ; et al.	2014-06-05
Methods for fabricating integrated circuits having low resistance device contacts Grant 8,691,689 - Besser , et al. April 8, 2	2014-04-08
Properties of metallic copper diffusion barriers through silicon surface treatments Grant 8,211,794 - Arunachalam , et al. July 3, 2	2012-07-03
Scalability With Reduced Contact Resistance App 20110204518 - Arunachalam; Valli	2011-08-25
MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME App 20090127594 - ARUNACHALAM; Valli ; et al.	2009-05-21
Properties Of Metallic Copper Diffusion Barriers Through Silicon Surface Treatments App 20080290515 - Arunachalam; Valli ; et al.	2008-11-27
Method for forming magnetic clad bit line App 20040087163 - Steimle, Robert ; et al.	2004-05-06

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