Arthur; John V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arthur; John V..The latest application filed is for "neural network weight distribution from a grid of memory elements".

Company Profile

55.78.93

Arthur; John V. - Mountain View CA
Arthur; John V. - San Jose CA
Arthur; John V. - Mountian View CA
Arthur; John V. - New Windsor NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hardware architecture for simulating a neural network of neurons Grant 11,341,401 - Alvarez-Icaza Rivera , et al. May 24, 2	2022-05-24
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 11,295,201 - Arthur , et al. April 5, 2	2022-04-05
Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine Grant 11,270,196 - Sawada , et al. March 8, 2	2022-03-08
Compound instruction set architecture for a neural inference chip Grant 11,263,011 - Cassidy , et al. March 1, 2	2022-03-01
Data distribution in an array of neural network cores Grant 11,238,347 - Taba , et al. February 1, 2	2022-02-01
Scalable neural hardware for the noisy-OR model of Bayesian networks Grant 11,238,343 - Arthur , et al. February 1, 2	2022-02-01
Hardware-software co-design of neurosynaptic systems Grant 11,200,496 - Arthur , et al. December 14, 2	2021-12-14
Yield tolerance in a neurosynaptic system Grant 11,184,221 - Alvarez-Icaza Rivera , et al. November 23, 2	2021-11-23
Neural Network Weight Distribution From A Grid Of Memory Elements App 20210312305 - Sawada; Jun ; et al.	2021-10-07
Providing transposable access to a synapse array using a recursive array layout Grant 11,074,496 - Arthur , et al. July 27, 2	2021-07-27
Compressed Weight Distribution In Networks Of Neural Processors App 20210209450 - Cassidy; Andrew S. ; et al.	2021-07-08
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network Grant 11,049,001 - Alvarez-Icaza Rivera , et al. June 29, 2	2021-06-29
Flexible Precision Neural Inference Processing Unit App 20210174176 - Cassidy; Andrew S. ; et al.	2021-06-10
Event-based Neural Network With Hierarchical Addressing For Routing Event Packets Between Core Circuits Of The Neural Network App 20210166107 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2021-06-03
Massively parallel neural inference computing elements Grant 11,010,662 - Appuswamy , et al. May 18, 2	2021-05-18
3d Neural Inference Processing Unit Architectures App 20210125040 - Cassidy; Andrew S. ; et al.	2021-04-29
Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency Grant 10,990,872 - Akopyan , et al. April 27, 2	2021-04-27
Peripheral device interconnections for neurosynaptic systems Grant 10,984,307 - Akopyan , et al. April 20, 2	2021-04-20
Multi-mode Low-precision Inner-product Computation Circuits For Massively Parallel Neural Inference Engine App 20210110245 - Sawada; Jun ; et al.	2021-04-15
Dual deterministic and stochastic neurosynaptic core circuit Grant 10,929,747 - Alvarez-Icaza , et al. February 23, 2	2021-02-23
Performing Error Detection During Deterministic Program Execution App 20200379841 - Cassidy; Andrew S. ; et al.	2020-12-03
Globally Asynchronous And Locally Synchronous (gals) Neuromorphic Network App 20200364535 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2020-11-19
Globally asynchronous and locally synchronous (GALS) neuromorphic network Grant 10,839,287 - Alvarez-Icaza Rivera , et al. November 17, 2	2020-11-17
Memory-mapped interface to message-passing computing systems Grant 10,838,860 - Akopyan , et al. November 17, 2	2020-11-17
Performing error detection during deterministic program execution Grant 10,831,595 - Cassidy , et al. November 10, 2	2020-11-10
Scaling multi-core neurosynaptic networks across chip boundaries Grant 10,785,745 - Alvarez Icaza Rivera , et al. Sept	2020-09-22
Converting digital numeric data to spike event data Grant 10,769,519 - Alvarez-Icaza Rivera , et al. Sep	2020-09-08
Converting spike event data to digital numeric data Grant 10,755,165 - Alvarez-Icaza Rivera , et al. A	2020-08-25
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array Grant 10,740,282 - Rivera , et al. A	2020-08-11
Multiplexing physical neurons to optimize power and area Grant 10,713,561 - Alvarez-Icaza Rivera , et al.	2020-07-14
Massively Parallel Neural Inference Computing Elements App 20200202205 - Appuswamy; Rathinakumar ; et al.	2020-06-25
Compound Instruction Set Architecture For A Neural Inference Chip App 20200167158 - Cassidy; Andrew S. ; et al.	2020-05-28
Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation Grant 10,650,301 - Alvarez-Icaza Rivera , et al.	2020-05-12
Networks For Distributing Parameters And Data To Neural Network Compute Cores App 20200117988 - Arthur; John V. ; et al.	2020-04-16
Data Representation For Dynamic Precision In Neural Network Cores App 20200117981 - Arthur; John V. ; et al.	2020-04-16
Multi-agent Instruction Execution Engine For Neural Inference Processing App 20200117465 - Cassidy; Andrew S. ; et al.	2020-04-16
Massively parallel neural inference computing elements Grant 10,621,489 - Appuswamy , et al.	2020-04-14
Data Distribution In An Array Of Neural Network Cores App 20200104718 - Taba; Brian ; et al.	2020-04-02
Neuromorphic Event-driven Neural Computing Architecture In A Scalable Neural Network App 20200065658 - Akopyan; Filipp ; et al.	2020-02-27
Scheduler For Mapping Neural Networks Onto An Array Of Neural Cores In An Inference Processing Unit App 20200042856 - Datta; Pallab ; et al.	2020-02-06
Hierarchical Parallelism In A Network Of Distributed Neural Network Cores App 20200019836 - Arthur; John V. ; et al.	2020-01-16
Instruction Distribution In An Array Of Neural Network Cores App 20200012929 - Penner; Hartmut ; et al.	2020-01-09
Memory-mapped Interface To Message-passing Computing Systems App 20200004678 - Akopyan; Filipp A. ; et al.	2020-01-02
Runtime Reconfigurable Neural Network Processor Core App 20190385048 - Cassidy; Andrew S. ; et al.	2019-12-19
Parallel Computational Architecture With Reconfigurable Core-level And Vector-level Parallelism App 20190385046 - Cassidy; Andrew S. ; et al.	2019-12-19
Neuromorphic event-driven neural computing architecture in a scalable neural network Grant 10,504,021 - Akopyan , et al. Dec	2019-12-10
Yield Tolerance In A Neurosynaptic System App 20190372831 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2019-12-05
Central Scheduler And Instruction Dispatcher For A Neural Inference Processor App 20190332924 - Cassidy; Andrew S. ; et al.	2019-10-31
Time, Space, And Energy Efficient Neural Inference Via Parallelism And On-chip Memory App 20190325295 - Modha; Dharmendra S. ; et al.	2019-10-24
Yield tolerance in a neurosynaptic system Grant 10,454,759 - Alvarez-Icaza Rivera , et al. Oc	2019-10-22
Memory-mapped interface for message passing computing systems Grant 10,452,540 - Akopyan , et al. Oc	2019-10-22
Massively Parallel Neural Inference Computing Elements App 20190303749 - Appuswamy; Rathinakumar ; et al.	2019-10-03
Defect Resistant Designs For Location-sensitive Neural Network Processor Arrays App 20190303741 - Appuswamy; Rathinakumar ; et al.	2019-10-03
Block Transfer Of Neuron Output Values Through Data Memory For Neurosynaptic Processors App 20190303740 - Arthur; John V. ; et al.	2019-10-03
Peripheral Device Interconnections For Neurosynaptic Systems App 20190294950 - Akopyan; Filipp A. ; et al.	2019-09-26
Peripheral device interconnections for neurosynaptic systems Grant 10,410,109 - Akopyan , et al. Sept	2019-09-10
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20190228289 - Arthur; John V. ; et al.	2019-07-25
Hardware Architecture For Simulating A Neural Network Of Neurons App 20190197394 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2019-06-27
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 10,331,998 - Arthur , et al.	2019-06-25
Scalable Neural Hardware For The Noisy-or Model Of Bayesian Networks App 20190156209 - Arthur; John V. ; et al.	2019-05-23
Hardware architecture for simulating a neural network of neurons Grant 10,282,658 - Alvarez-Icaza Rivera , et al.	2019-05-07
Hardware-software Co-design Of Neurosynaptic Systems App 20190122114 - Arthur; John V. ; et al.	2019-04-25
Memory-mapped Interface For Message Passing Computing Systems App 20190121734 - Akopyan; Filipp A. ; et al.	2019-04-25
Mapping neural dynamics of a neural model on to a coarsely grained look-up table Grant 10,204,118 - Alvarez-Icaza Rivera , et al. Feb	2019-02-12
Scalable neural hardware for the noisy-OR model of Bayesian networks Grant 10,198,692 - Arthur , et al. Fe	2019-02-05
Faulty core recovery mechanisms for a three-dimensional network on a processor array Grant 10,176,063 - Alvarez-Icaza Rivera , et al. J	2019-01-08
Neuromorphic network comprising asynchronous routers and synchronous core circuits Grant 10,169,700 - Alvarez-Icaza Rivera , et al. J	2019-01-01
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network Grant 10,102,474 - Alvarez-Icaza Rivera , et al. October 16, 2	2018-10-16
Yield Tolerance In A Neurosynaptic System App 20180287862 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2018-10-04
Dual Deterministic And Stochastic Neurosynaptic Core Circuit App 20180232634 - Alvarez-Icaza; Rodrigo ; et al.	2018-08-16
Providing Transposable Access To A Synapse Array Using A Recursive Array Layout App 20180211163 - Arthur; John V. ; et al.	2018-07-26
Yield tolerance in a neurosynaptic system Grant 9,992,057 - Alvarez-Icaza Rivera , et al. June 5, 2	2018-06-05
Dual deterministic and stochastic neurosynaptic core circuit Grant 9,984,324 - Alvarez-Icaza , et al. May 29, 2	2018-05-29
Providing transposable access to a synapse array using a recursive array layout Grant 9,965,718 - Arthur , et al. May 8, 2	2018-05-08
Mapping Neural Dynamics Of A Neural Model On To A Coarsely Grained Look-up Table App 20180113885 - ALVAREZ-ICAZA RIVERA; RODRIGO ; et al.	2018-04-26
Scaling Multi-core Neurosynaptic Networks Across Chip Boundaries App 20180103448 - Alvarez Icaza Rivera; Rodrigo ; et al.	2018-04-12
Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array Grant 9,940,302 - Alvarez-Icaza Rivera , et al. April 10, 2	2018-04-10
Converting Spike Event Data To Digital Numeric Data App 20180082174 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2018-03-22
Converting Digital Numeric Data To Spike Event Data App 20180082173 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2018-03-22
Scaling multi-core neurosynaptic networks across chip boundaries Grant 9,924,490 - Alvarez Icaza Rivera , et al. March 20, 2	2018-03-20
Converting spike event data to digital numeric data Grant 9,886,662 - Alvarez-Icaza Rivera , et al. February 6, 2	2018-02-06
Converting digital numeric data to spike event data Grant 9,881,252 - Alvarez-Icaza Rivera , et al. January 30, 2	2018-01-30
Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits Grant 9,852,006 - Akopyan , et al. December 26, 2	2017-12-26
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation Grant 9,818,058 - Arthur , et al. November 14, 2	2017-11-14
Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs Grant 9,797,946 - Alvarez-Icaza Rivera , et al. October 24, 2	2017-10-24
Array of processor core circuits with reversible tiers Grant 9,792,251 - Alvarez-Icaza Rivera , et al. October 17, 2	2017-10-17
Energy-efficient Time-multiplexed Neurosynaptic Core For Implementing Neural Networks Spanning Power- And Area-efficiency App 20170286825 - Akopyan; Filipp A. ; et al.	2017-10-05
Self-timed, event-driven neurosynaptic core controller Grant 9,747,545 - Akopyan , et al. August 29, 2	2017-08-29
Initializing And Testing Integrated Circuits With Selectable Scan Chains With Exclusive-or Outputs App 20170199241 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2017-07-13
Array Of Processor Core Circuits With Reversible Tiers App 20170124024 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2017-05-04
Globally Asynchronous And Locally Synchronous (gals) Neuromorphic Network App 20170076197 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2017-03-16
Dual Deterministic And Stochastic Neurosynaptic Core Circuit App 20170068885 - Alvarez-Icaza; Rodrigo ; et al.	2017-03-09
Array of processor core circuits with reversible tiers Grant 9,588,937 - Alvarez-Icaza Rivera , et al. March 7, 2	2017-03-07
Globally asynchronous and locally synchronous (GALS) neuromorphic network Grant 9,563,841 - Alvarez-Icaza Rivera , et al. February 7, 2	2017-02-07
Dual deterministic and stochastic neurosynaptic core circuit Grant 9,558,443 - Alvarez-Icaza , et al. January 31, 2	2017-01-31
Hardware Architecture For Simulating A Neural Network Of Neurons App 20160358066 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-12-08
Yield Tolerance In A Neurosynaptic System App 20160323137 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-11-03
Consolidating Multiple Neurosynaptic Core Circuits Into One Reconfigurable Memory Block App 20160321537 - Akopyan; Filipp A. ; et al.	2016-11-03
Event-based Neural Network With Hierarchical Addressing App 20160321539 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-11-03
Hardware architecture for simulating a neural network of neurons Grant 9,466,022 - Alvarez-Icaza Rivera , et al. October 11, 2	2016-10-11
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Universal Substrate Of Adaptation App 20160260008 - Arthur; John V. ; et al.	2016-09-08
Mapping neural dynamics of a neural model on to a coarsely grained look-up table Grant 9,424,284 - Alvarez-Icaza Rivera , et al. August 23, 2	2016-08-23
Faulty Core Recovery Mechanisms For A Three-dimensional Network On A Processor Array App 20160239393 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-08-18
Scaling Multi-core Neurosynaptic Networks Across Chip Boundaries App 20160224889 - Alvarez Icaza Rivera; Rodrigo ; et al.	2016-08-04
Neuromorphic Event-driven Neural Computing Architecture In A Scalable Neural Network App 20160224886 - Akopyan; Filipp ; et al.	2016-08-04
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation Grant 9,373,073 - Arthur , et al. June 21, 2	2016-06-21
Faulty core recovery mechanisms for a three-dimensional network on a processor array Grant 9,363,137 - Alvarez-Icaza Rivera , et al. June 7, 2	2016-06-07
Faulty Core Recovery Mechanisms For A Three-dimensional Network On A Processor Array App 20160154717 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-06-02
Interconnect Circuits At Three-dimensional (3-d) Bonding Interfaces Of A Processor Array App 20160148901 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-05-26
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20160110640 - Arthur; John V. ; et al.	2016-04-21
Converting Digital Numeric Data To Spike Event Data App 20160086075 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-03-24
Converting Spike Event Data To Digital Numeric Data App 20160086076 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-03-24
Self-timed, Event-driven Neurosynaptic Core Controller App 20160086077 - Akopyan; Filipp A. ; et al.	2016-03-24
Peripheral Device Interconnections For Neurosynaptic Systems App 20160055408 - Akopyan; Filipp A. ; et al.	2016-02-25
Neuromorphic event-driven neural computing architecture in a scalable neural network Grant 9,269,044 - Akopyan , et al. February 23, 2	2016-02-23
Hardware Architecture For Simulating A Neural Network Of Neurons App 20160034808 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2016-02-04
Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs Grant 9,244,124 - Alvarez-Icaza Rivera , et al. January 26, 2	2016-01-26
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 9,239,984 - Arthur , et al. January 19, 2	2016-01-19
Scalable Neural Hardware For The Noisy-or Model Of Bayesian Networks App 20150379398 - Arthur; John V. ; et al.	2015-12-31
Multiplexing Physical Neurons To Optimize Power And Area App 20150379393 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2015-12-31
Providing Transposable Access To A Synapse Array Using A Recursive Array Layout App 20150379396 - Arthur; John V. ; et al.	2015-12-31
Providing transposable access to a synapse array using a recursive array layout Grant 9,218,564 - Arthur , et al. December 22, 2	2015-12-22
Scalable neural hardware for the noisy-OR model of Bayesian networks Grant 9,189,729 - Arthur , et al. November 17, 2	2015-11-17
Neuromorphic Hardware For Neuronal Computation And Non-neuronal Computation App 20150324684 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2015-11-12
Globally Asynchronous And Locally Synchronous (gals) Neuromorphic Network App 20150302295 - Rivera; Rodrigo Alvarez-Icaza ; et al.	2015-10-22
Multiplexing physical neurons to optimize power and area Grant 9,159,020 - Alcarez-Icaza Rivera , et al. October 13, 2	2015-10-13
Faulty core recovery mechanisms for a three-dimensional network on a processor array Grant 9,160,617 - Alvarez-Icaza Rivera , et al. October 13, 2	2015-10-13
Providing Transposable Access To A Synapse Array Using A Recursive Array Layout App 20150286923 - Arthur; John V. ; et al.	2015-10-08
Scalable Neural Hardware For The Noisy-or Model Of Bayesian Networks App 20150286924 - Arthur; John V. ; et al.	2015-10-08
Initializing And Testing Integrated Circuits With Selectable Scan Chains With Exclusive-or Outputs App 20150276867 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2015-10-01
Neuromorphic Event-driven Neural Computing Architecture In A Scalable Neural Network App 20150262055 - Akopyan; Filipp ; et al.	2015-09-17
Multiplexing Physical Neurons To Optimize Power And Area App 20150254551 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2015-09-10
Mapping Neural Dynamics Of A Neural Model On To A Coarsely Grained Look-up Table App 20150227558 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2015-08-13
Hardware architecture for simulating a neural network of neurons Grant 9,087,301 - Alvarez-Icaza Rivera , et al. July 21, 2	2015-07-21
Mapping neural dynamics of a neural model on to a coarsely grained look-up table Grant 9,053,429 - Alvarez-Icaza Rivera , et al. June 9, 2	2015-06-09
Consolidating multiple neurosynaptic cores into one memory Grant 8,990,130 - Alvarez-Icaza Rivera , et al. March 24, 2	2015-03-24
Final faulty core recovery mechanisms for a two-dimensional network on a processor array Grant 8,990,616 - Alvarez-Icaza Rivera , et al. March 24, 2	2015-03-24
Dual Deterministic And Stochastic Neurosynaptic Core Circuit App 20150039546 - Alvarez-Icaza; Rodrigo ; et al.	2015-02-05
Providing transposable access to a synapse array using column aggregation Grant 8,918,351 - Arthur , et al. December 23, 2	2014-12-23
Neuromorphic event-driven neural computing architecture in a scalable neural network Grant 8,909,576 - Akopyan , et al. December 9, 2	2014-12-09
Providing Transposable Access To A Synapse Array Using Column Aggregation App 20140344201 - Arthur; John V. ; et al.	2014-11-20
Array Of Processor Core Circuits With Reversible Tiers App 20140244971 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-08-28
Low-power event-driven neural computing architecture in neural networks Grant 8,812,414 - Arthur , et al. August 19, 2	2014-08-19
Consolidating Multiple Neurosynaptic Cores Into One Memory App 20140222740 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-08-07
Hardware Architecture For Simulating A Neural Network Of Neurons App 20140180988 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-06-26
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20140180987 - Arthur; John V. ; et al.	2014-06-26
Mapping Neural Dynamics Of A Neural Model On To A Coarsely Grained Look-up Table App 20140180985 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-06-26
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Universal Substrate Of Adaptation App 20140180984 - Arthur; John V. ; et al.	2014-06-26
Low-power Event-driven Neural Computing Architecture In Neural Networks App 20140114893 - Arthur; John V. ; et al.	2014-04-24
Faulty Core Recovery Mechanisms For A Three-dimensional Network On A Processor Array App 20140092728 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-04-03
Final Faulty Core Recovery Mechanisms For A Two-dimensional Network On A Processor Array App 20140095923 - Alvarez-Icaza Rivera; Rodrigo ; et al.	2014-04-03
Integrate and fire electronic neurons Grant 8,473,439 - Arthur , et al. June 25, 2	2013-06-25
Neuromorphic Event-driven Neural Computing Architecture In A Scalable Neural Network App 20130073497 - Akopyan; Filipp ; et al.	2013-03-21
Integrate And Fire Electronic Neurons App 20120150781 - Arthur; John V. ; et al.	2012-06-14