Arora; Sampan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arora; Sampan.The latest application filed is for "system and method for re-shuffling test case instruction orders for processor design verification and validation".

Company Profile

0.5.5

Arora; Sampan - Bangalore IN
Arora; Sampan - Karnataka IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode Grant 8,127,192 - Arora , et al. February 28, 2	2012-02-28
System and method for testing multiple processor modes for processor design verification and validation Grant 8,006,221 - Arora , et al. August 23, 2	2011-08-23
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation Grant 7,689,886 - Arora , et al. March 30, 2	2010-03-30
System and method for re-shuffling test case instruction orders for processor design verification and validation Grant 7,669,083 - Arora , et al. February 23, 2	2010-02-23
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation Grant 7,661,023 - Arora , et al. February 9, 2	2010-02-09
System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation App 20090070631 - Arora; Sampan ; et al.	2009-03-12
System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation App 20090070629 - Arora; Sampan ; et al.	2009-03-12
System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation App 20090024886 - Arora; Sampan ; et al.	2009-01-22
System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation App 20090024876 - Arora; Sampan ; et al.	2009-01-22
System And Method For Predicting Iwarx And Stwcx Instructions In Test Pattern Generation And Simulation For Processor Design Verification/validation In Interrupt Mode App 20090024894 - Arora; Sampan ; et al.	2009-01-22

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