| Patent | Date |
|---|
Method for creating barriers for copper diffusion
Grant 7,829,455 - Zubkov , et al. November 9, 2 | 2010-11-09 |
Method of treating metal and metal salts to enable thin layer deposition in semiconductor processing
Grant 7,670,645 - Aronowitz , et al. March 2, 2 | 2010-03-02 |
Method of vaporizing and ionizing metals for use in semiconductor processing
Grant 7,323,228 - Aronowitz , et al. January 29, 2 | 2008-01-29 |
Method and apparatus for forming a memory structure having an electron affinity region
Grant 7,132,336 - Aronowitz , et al. November 7, 2 | 2006-11-07 |
Method for creating barriers for copper diffusion
Grant 7,115,991 - Zubkov , et al. October 3, 2 | 2006-10-03 |
Vaporization and ionization of metals for use in semiconductor processing
Grant 7,084,408 - Kimball , et al. August 1, 2 | 2006-08-01 |
Method for growing thin films
Grant 7,081,296 - Aronowitz , et al. July 25, 2 | 2006-07-25 |
Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
Grant 7,015,168 - Aronowitz , et al. March 21, 2 | 2006-03-21 |
Memory device having an electron trapping layer in a high-K dielectric gate stack
Grant 6,989,565 - Aronowitz , et al. January 24, 2 | 2006-01-24 |
Memory device having an electron trapping layer in a high-K dielectric gate stack
App 20050258475 - Aronowitz, Sheldon ; et al. | 2005-11-24 |
Method for creating barriers for copper diffusion
App 20050179138 - Zubkov, Vladimir ; et al. | 2005-08-18 |
Calcium doped polysilicon gate electrodes
Grant 6,930,362 - Mirabedini , et al. August 16, 2 | 2005-08-16 |
High-K dielectric gate material uniquely formed
Grant 6,919,263 - Aronowitz , et al. July 19, 2 | 2005-07-19 |
Process to minimize polysilicon gate depletion and dopant penetration and to increase conductivity
Grant 6,897,102 - Aronowitz , et al. May 24, 2 | 2005-05-24 |
Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
App 20050098856 - Aronowitz, Sheldon ; et al. | 2005-05-12 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material
Grant 6,858,195 - Aronowitz , et al. February 22, 2 | 2005-02-22 |
Integrated circuit isolation system
Grant 6,831,348 - Puchner , et al. December 14, 2 | 2004-12-14 |
Method of chemically altering a silicon surface and associated electrical devices
Grant 6,822,308 - Aronowitz , et al. November 23, 2 | 2004-11-23 |
Method for growing thin films
App 20040175947 - Aronowitz, Sheldon ; et al. | 2004-09-09 |
Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate
Grant 6,759,337 - Aronowitz , et al. July 6, 2 | 2004-07-06 |
Method for creating barriers to metal contamination in silicon oxides
App 20040121550 - Zubkov, Vladimir ; et al. | 2004-06-24 |
Process to minimize polysilicon gate depletion and dopant penetration and to increase conductivity
App 20040110328 - Aronowitz, Sheldon ; et al. | 2004-06-10 |
Self-aligned alloy capping layers for copper interconnect structures
Grant 6,747,358 - Rissman , et al. June 8, 2 | 2004-06-08 |
Method for growing thin films
Grant 6,743,474 - Aronowitz , et al. June 1, 2 | 2004-06-01 |
High-K dielectric gate material uniquely formed
App 20040089887 - Aronowitz, Sheldon ; et al. | 2004-05-13 |
Method for reticle formation utilizing metal vaporization
Grant 6,673,498 - Aronowitz , et al. January 6, 2 | 2004-01-06 |
Method of chemically altering a silicon surface and associated electrical devices
App 20030235988 - Aronowitz, Sheldon ; et al. | 2003-12-25 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
Grant 6,649,219 - Aronowitz , et al. November 18, 2 | 2003-11-18 |
Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
App 20030207750 - Zubkov, Vladimir ; et al. | 2003-11-06 |
Method of chemically altering a silicon surface and associated electrical devices
Grant 6,627,556 - Aronowitz , et al. September 30, 2 | 2003-09-30 |
Integrated circuit isolation system
Grant 6,613,651 - Puchner , et al. September 2, 2 | 2003-09-02 |
Integrated circuit isolation system
App 20030162366 - Puchner, Helmut ; et al. | 2003-08-28 |
Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material
Grant 6,572,925 - Zubkov , et al. June 3, 2 | 2003-06-03 |
Method for creating self-aligned alloy capping layers for copper interconnect structures
Grant 6,566,262 - Rissman , et al. May 20, 2 | 2003-05-20 |
Process for forming high dielectric constant gate dielectric for integrated circuit structure
Grant 6,511,925 - Aronowitz , et al. January 28, 2 | 2003-01-28 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
App 20020119326 - Zubkov, Vladimir ; et al. | 2002-08-29 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
App 20020119315 - Aronowitz, Sheldon ; et al. | 2002-08-29 |
Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
App 20020117082 - Aronowitz, Sheldon ; et al. | 2002-08-29 |
Process For Forming Thin Gate Oxide With Enhanced Reliability By Nitridation Of Upper Surface Of Gate Of Oxide To Form Barrier Of Nitrogen Atoms In Upper Surface Region Of Gate Oxide, And Resulting Product
Grant 6,413,881 - Aronowitz , et al. July 2, 2 | 2002-07-02 |
Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
Grant 6,331,468 - Aronowitz , et al. December 18, 2 | 2001-12-18 |
Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same
Grant 6,303,047 - Aronowitz , et al. October 16, 2 | 2001-10-16 |
FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
Grant 6,180,470 - Aronowitz , et al. January 30, 2 | 2001-01-30 |
Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
Grant 6,156,620 - Puchner , et al. December 5, 2 | 2000-12-05 |
Modification of interfacial fields between dielectrics and semiconductors
Grant 6,117,749 - Aronowitz , et al. September 12, 2 | 2000-09-12 |
Composite semiconductor gate dielectrics
Grant 6,087,229 - Aronowitz , et al. July 11, 2 | 2000-07-11 |
Process for forming re-entrant geometry for gate electrode of integrated circuit structure
Grant 6,060,375 - Owyang , et al. May 9, 2 | 2000-05-09 |
Method of forming variable thickness gate dielectrics
Grant 6,033,998 - Aronowitz , et al. March 7, 2 | 2000-03-07 |
Method of forming retrograde well structures and punch-through barriers using low energy implants
Grant 5,963,801 - Aronowitz , et al. October 5, 1 | 1999-10-05 |
Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells
Grant 5,904,551 - Aronowitz , et al. May 18, 1 | 1999-05-18 |
Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation
Grant 5,877,530 - Aronowitz , et al. March 2, 1 | 1999-03-02 |
Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate
Grant 5,858,864 - Aronowitz , et al. January 12, 1 | 1999-01-12 |
Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same
Grant 5,837,598 - Aronowitz , et al. November 17, 1 | 1998-11-17 |
Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
Grant 5,723,896 - Yee , et al. March 3, 1 | 1998-03-03 |
Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device
Grant 5,585,286 - Aronowitz , et al. December 17, 1 | 1996-12-17 |
Defect free CMOS process
Grant 5,571,744 - Demirlioglu , et al. November 5, 1 | 1996-11-05 |
Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions
Grant 5,504,016 - Aronowitz April 2, 1 | 1996-04-02 |
Control and modification of dopant distribution and activation in polysilicon
Grant 5,468,974 - Aronowitz , et al. November 21, 1 | 1995-11-21 |
Gate array layout to accommodate multi angle ion implantation
Grant 5,459,085 - Pasen , et al. October 17, 1 | 1995-10-17 |
Defect-free bipolar process
Grant 5,453,389 - Strain , et al. September 26, 1 | 1995-09-26 |
CMOS latchup suppression by localized minority carrier lifetime reduction
Grant 5,441,900 - Bulucea , et al. August 15, 1 | 1995-08-15 |
CMOS latchup suppression by localized minority carrier lifetime reduction
Grant 5,384,477 - Bulucea , et al. January 24, 1 | 1995-01-24 |
Method for forming isolated semiconductor structures
Grant 5,376,560 - Aronowitz , et al. December 27, 1 | 1994-12-27 |
Method for forming isolated semiconductor structures
Grant 5,372,952 - Aronowitz , et al. December 13, 1 | 1994-12-13 |
Method of providing lower contact resistance in MOS transistors
Grant 5,312,766 - Aronowitz , et al. May 17, 1 | 1994-05-17 |
Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon
Grant 5,298,435 - Aronowitz , et al. March 29, 1 | 1994-03-29 |
Method of providing lower contact resistance in MOS transistor structures
Grant 5,296,386 - Aronowitz , et al. March 22, 1 | 1994-03-22 |
Method of providing lower contact resistance in MOS transistor structures
Grant 5,296,387 - Aronowitz , et al. March 22, 1 | 1994-03-22 |
Method of fabricating P-buried layers for PNP devices
Grant 5,137,838 - Ramde , et al. August 11, 1 | 1992-08-11 |
Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures
Grant 5,043,292 - Aronowitz , et al. August 27, 1 | 1991-08-27 |
Modification of properties of p-type dopants with other p-type dopants
Grant 4,746,964 - Aronowitz May 24, 1 | 1988-05-24 |
Method of controlling dopant diffusion and dopant electrical activation by implanted inert gas atoms
Grant 4,689,667 - Aronowitz August 25, 1 | 1987-08-25 |
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