Arimilli; Ravi Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arimilli; Ravi Kumar.The latest application filed is for "event-based dynamic resource provisioning".

Company Profile

0.200.126

Arimilli; Ravi Kumar - Austin TX US
Arimilli; Ravi Kumar - Round Rock TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Techniques for dynamically assigning jobs to processors in a cluster using local job tables Grant 9,396,021 - Arimilli , et al. July 19, 2	2016-07-19
Techniques for dynamically assigning jobs to processors in a cluster based on inter-thread communications Grant 9,384,042 - Arimilli , et al. July 5, 2	2016-07-05
Event-based dynamic resource provisioning Grant 8,977,752 - Arimilli , et al. March 10, 2	2015-03-10
Method and system for thread-based memory speculation in a memory subsystem of a data processing system Grant 8,892,821 - Arimilli , et al. November 18, 2	2014-11-18
Bulk power assembly Grant 8,754,546 - Arimilli , et al. June 17, 2	2014-06-17
Techniques for dynamically assigning jobs to processors in a cluster based on processor workload Grant 8,239,524 - Arimilli , et al. August 7, 2	2012-08-07
Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information Grant 8,122,132 - Arimilli , et al. February 21, 2	2012-02-21
Virtual controllers with a large data center Grant 8,028,017 - Arimilli , et al. September 27, 2	2011-09-27
Power conversion, control, and distribution system Grant 8,018,095 - Arimilli , et al. September 13, 2	2011-09-13
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states Grant 7,849,298 - Arimilli , et al. December 7, 2	2010-12-07
Virtual Controllers With A Large Data Center App 20100268755 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Bulk Power Assembly App 20100264733 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Event-based Dynamic Resource Provisioning App 20100269119 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Dynamic Runtime Modification of Array Layout for Offset App 20100268880 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Power Conversion, Control, And Distribution System App 20100264731 - Arimilli; Ravi Kumar ; et al.	2010-10-21
Method and data processing system for microprocessor communication in a cluster-based multi-processor system Grant 7,818,364 - Arimilli , et al. October 19, 2	2010-10-19
Cache coherent I/O communication Grant 7,783,842 - Arimilli , et al. August 24, 2	2010-08-24
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Inter-thread Communications App 20100153965 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Processor Workload App 20100153541 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Broadcast Information App 20100153542 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Using Local Job Tables App 20100153966 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Method and data processing system for processor-to-processor communication in a clustered multi-processor system Grant 7,734,877 - Arimilli , et al. June 8, 2	2010-06-08
Method, processing unit and data processing system for microprocessor communication in a multi-processor system Grant 7,698,373 - Arimilli , et al. April 13, 2	2010-04-13
Multiprocessor system with retry-less TLBI protocol Grant 7,617,378 - Arimilli , et al. November 10, 2	2009-11-10
Host Ethernet adapter for networking offload in server environment Grant 7,586,936 - Arimilli , et al. September 8, 2	2009-09-08
Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States App 20090157945 - Arimilli; Ravi Kumar ; et al.	2009-06-18
Data processing system with backplane and processor books configurable to support both technical and commercial workloads Grant 7,526,631 - Arimilli , et al. April 28, 2	2009-04-28
High speed memory cloning facility via a lockless multiprocessor mechanism Grant 7,502,917 - Arimilli , et al. March 10, 2	2009-03-10
System and method for completing full updates to entire cache lines stores with address-only bus operations Grant 7,493,446 - Arimilli , et al. February 17, 2	2009-02-17
Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system Grant 7,493,417 - Arimilli , et al. February 17, 2	2009-02-17
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states Grant 7,493,478 - Arimilli , et al. February 17, 2	2009-02-17
Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization Grant 7,475,399 - Arimilli , et al. January 6, 2	2009-01-06
Method and data processing system having dynamic profile-directed feedback at runtime Grant 7,448,037 - Arimilli , et al. November 4, 2	2008-11-04
Data Processing System With Backplane And Processor Books Configurable To Suppprt Both Technical And Commercial Workloads App 20080209163 - Arimilli; Ravi Kumar ; et al.	2008-08-28
Method And Data Processing System For Processor-to-processor Communication In A Clustered Multi-processor System App 20080155231 - Arimilli; Ravi Kumar ; et al.	2008-06-26
System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations App 20080140943 - Arimilli; Ravi Kumar ; et al.	2008-06-12
Method, Processing Unit And Data Processing System For Microprocessor Communication In A Multi-processor System App 20080109816 - ARIMILLI; RAVI KUMAR ; et al.	2008-05-08
Method And Data Processing System For Microprocessor Communication In A Cluster-based Multi-processor System App 20080091918 - Arimilli; Ravi Kumar ; et al.	2008-04-17
System and method for completing updates to entire cache lines with address-only bus operations Grant 7,360,021 - Arimilli , et al. April 15, 2	2008-04-15
Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network Grant 7,360,067 - Arimilli , et al. April 15, 2	2008-04-15
Method and data processing system for microprocessor communication in a cluster-based multi-processor system Grant 7,359,932 - Arimilli , et al. April 15, 2	2008-04-15
Method, processing unit and data processing system for microprocessor communication in a multi-processor system Grant 7,356,568 - Arimilli , et al. April 8, 2	2008-04-08
Multiprocessor data processing system having scalable data interconnect and data routing mechanism Grant 7,308,558 - Arimilli , et al. December 11, 2	2007-12-11
System bus read data transfers with data ordering control bits Grant 7,308,536 - Arimilli , et al. December 11, 2	2007-12-11
Cross partition sharing of state information Grant 7,272,664 - Arimilli , et al. September 18, 2	2007-09-18
High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system Grant 7,213,248 - Arimilli , et al. May 1, 2	2007-05-01
Host ethernet adapter for networking offload in server environment App 20060251120 - Arimilli; Ravi Kumar ; et al.	2006-11-09
Method and system for supplier-based memory speculation in a memory subsystem of a data processing system Grant 7,130,967 - Arimilli , et al. October 31, 2	2006-10-31
Data processing system and method with dynamic idle for tunable interface calibration Grant 7,117,126 - Floyd , et al. October 3, 2	2006-10-03
Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components Grant 7,117,388 - Arimilli , et al. October 3, 2	2006-10-03
Managing processor architected state upon an interrupt Grant 7,117,319 - Arimilli , et al. October 3, 2	2006-10-03
System and method to stall dispatch of gathered store operations in a store queue using a timer Grant 7,089,364 - Arimilli , et al. August 8, 2	2006-08-08
Method and data processing system for microprocessor communication in a cluster-based multi-processor network Grant 7,073,004 - Arimilli , et al. July 4, 2	2006-07-04
Multiprocessor system supporting multiple outstanding TLBI operations per partition Grant 7,073,043 - Arimilli , et al. July 4, 2	2006-07-04
Dynamic data routing mechanism for a high speed memory cloner Grant 7,069,394 - Arimilli , et al. June 27, 2	2006-06-27
Data processing system providing hardware acceleration of input/output (I/O) communication Grant 7,047,320 - Arimilli , et al. May 16, 2	2006-05-16
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems Grant 7,039,832 - Arimilli , et al. May 2, 2	2006-05-02
Programming means for dynamic specifications of cache management preferences Grant 7,039,760 - Arimilli , et al. May 2, 2	2006-05-02
Method, apparatus and system for managing released promotion bits Grant 7,017,031 - Arimilli , et al. March 21, 2	2006-03-21
Data processing system having no system memory Grant 7,017,024 - Arimilli , et al. March 21, 2	2006-03-21
Multiprocessor data processing system having a data routing mechanism regulated through control communication Grant 7,007,128 - Arimilli , et al. February 28, 2	2006-02-28
High speed memory cloning facility via a source/destination switching mechanism Grant 6,996,693 - Arimilli , et al. February 7, 2	2006-02-07
Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP Grant 6,990,545 - Arimilli , et al. January 24, 2	2006-01-24
Imprecise cache line protection mechanism during a memory clone operation Grant 6,986,013 - Arimilli , et al. January 10, 2	2006-01-10
High speed memory cloner within a data processing system Grant 6,986,011 - Arimilli , et al. January 10, 2	2006-01-10
Dynamically managing saved processor soft states Grant 6,983,347 - Arimilli , et al. January 3, 2	2006-01-03
Processor virtualization mechanism via an enhanced restoration of hard architected states Grant 6,981,083 - Arimilli , et al. December 27, 2	2005-12-27
Acceleration of input/output (I/O) communication through improved address translation Grant 6,976,148 - Arimilli , et al. December 13, 2	2005-12-13
Layered local cache with lower level cache optimizing allocation mechanism Grant 6,970,976 - Arimilli , et al. November 29, 2	2005-11-29
Method to stall store operations to increase chances of gathering full entries for updating cachelines App 20050251622 - Arimilli, Ravi Kumar ; et al.	2005-11-10
Method for completing full cacheline stores with address-only bus operations App 20050251623 - Arimilli, Ravi Kumar ; et al.	2005-11-10
System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture Grant 6,963,967 - Guthrie , et al. November 8, 2	2005-11-08
Asynchronous non-blocking snoop invalidation Grant 6,944,721 - Arimilli , et al. September 13, 2	2005-09-13
System bus read data transfers with data ordering control bits App 20050193174 - Arimilli, Ravi Kumar ; et al.	2005-09-01
Data processing system with naked cache line write operations Grant 6,928,524 - Arimilli , et al. August 9, 2	2005-08-09
Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction Grant 6,925,551 - Arimilli , et al. August 2, 2	2005-08-02
Method and system of managing virtualized physical memory in a data processing system Grant 6,920,521 - Arimilli , et al. July 19, 2	2005-07-19
Method, apparatus and system that cache promotion information within a processor separate from instructions and data Grant 6,920,514 - Arimilli , et al. July 19, 2	2005-07-19
Method and data processing system having dynamic profile-directed feedback at runtime App 20050154861 - Arimilli, Ravi Kumar ; et al.	2005-07-14
Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization App 20050154860 - Arimilli, Ravi Kumar ; et al.	2005-07-14
Multiprocessor data processing system having a data routing mechanism regulated through control communication App 20050149660 - Arimilli, Ravi Kumar ; et al.	2005-07-07
Multiprocessor data processing system having scalable data interconnect and data routing mechanism App 20050149692 - Arimilli, Ravi Kumar ; et al.	2005-07-07
High speed memory cloning facility via a coherently done mechanism Grant 6,915,390 - Arimilli , et al. July 5, 2	2005-07-05
Method and apparatus for transmitting packets within a symmetric multiprocessor system Grant 6,910,062 - Arimilli , et al. June 21, 2	2005-06-21
Method and system for thread-based memory speculation in a memory subsystem of a data processing system App 20050132148 - Arimilli, Ravi Kumar ; et al.	2005-06-16
Method and system for supplier-based memory speculation in a memory subsystem of a data processing system App 20050132147 - Arimilli, Ravi Kumar ; et al.	2005-06-16
Method and system of managing virtualized physical memory in a memory controller and processor system Grant 6,907,494 - Arimilli , et al. June 14, 2	2005-06-14
Method and system of managing virtualized physical memory in a multi-processor system Grant 6,904,490 - Arimilli , et al. June 7, 2	2005-06-07
Memory directory management in a multi-node computer system Grant 6,901,485 - Arimilli , et al. May 31, 2	2005-05-31
Dynamic software accessibility to a microprocessor system with a high speed memory cloner Grant 6,898,677 - Arimilli , et al. May 24, 2	2005-05-24
High speed memory cloner with extended cache coherency protocols and responses Grant 6,892,283 - Arimilli , et al. May 10, 2	2005-05-10
Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system Grant 6,886,079 - Arimilli , et al. April 26, 2	2005-04-26
Speculative execution of instructions and processes before completion of preceding barrier operations Grant 6,880,073 - Arimilli , et al. April 12, 2	2005-04-12
System bus read data transfers with data ordering control bits Grant 6,874,063 - Arimilli , et al. March 29, 2	2005-03-29
Data processing system having a physically addressed cache of disk memory App 20050055528 - Arimilli, Ravi Kumar ; et al.	2005-03-10
Robust system bus recovery Grant 6,865,695 - Joyner , et al. March 8, 2	2005-03-08
Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response Grant 6,848,003 - Arimilli , et al. January 25, 2	2005-01-25
Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction Grant 6,842,847 - Arimilli , et al. January 11, 2	2005-01-11
Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system Grant 6,829,762 - Arimilli , et al. December 7, 2	2004-12-07
Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction Grant 6,829,698 - Arimilli , et al. December 7, 2	2004-12-07
Cache invalidation bus for a highly scalable shared cache memory hierarchy Grant 6,826,654 - Arimilli , et al. November 30, 2	2004-11-30
Apparatus for imprecisely tracking cache line inclusivity of a higher level cache Grant 6,826,655 - Arimilli , et al. November 30, 2	2004-11-30
Processor book for building large scalable processor systems App 20040236891 - Arimilli, Ravi Kumar ; et al.	2004-11-25
Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem Grant 6,823,471 - Arimilli , et al. November 23, 2	2004-11-23
Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components App 20040230731 - Arimilli, Ravi Kumar ; et al.	2004-11-18
Local invalidation buses for a highly scalable shared cache memory hierarchy Grant 6,813,694 - Arimilli , et al. November 2, 2	2004-11-02
Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP App 20040215865 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Method and data processing system for microprocessor communication in a cluster-based multi-processor network App 20040215899 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Data processing system having novel interconnect for supporting both technical and commercial workloads App 20040215926 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Non-disruptive, dynamic hot-add and hot-remove of non-symmetric data processing system resources App 20040215864 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Multiprocessor system with retry-less TLBI protocol App 20040215897 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Programming means for dynamic specifications of cache management preferences App 20040215888 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Multiprocessor system supporting multiple outstanding TLBI operations per partition App 20040215898 - Arimilli, Ravi Kumar ; et al.	2004-10-28
Imprecise snooping based invalidation mechanism Grant 6,801,984 - Arimilli , et al. October 5, 2	2004-10-05
DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism Grant 6,785,776 - Arimilli , et al. August 31, 2	2004-08-31
High performance symmetric multiprocessing systems via super-coherent data mechanisms Grant 6,785,774 - Arimilli , et al. August 31, 2	2004-08-31
Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism Grant 6,782,456 - Arimilli , et al. August 24, 2	2004-08-24
Symmetric multiprocessor systems with an independent super-coherent cache directory Grant 6,779,086 - Arimilli , et al. August 17, 2	2004-08-17
Data processing system providing hardware acceleration of input/outpuit (I/O) communication App 20040139246 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Cache coherent I/O communication App 20040139283 - Arimilli, Ravi Kumar ; et al.	2004-07-15
High speed virtual instruction execution mechanism App 20040139304 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Hardware-enabled instruction tracing App 20040139305 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Acceleration of input/output (I/O) communication through improved address translation App 20040139295 - Arimilli, Ravi Kumar ; et al.	2004-07-15
Data processing system and method for resolving a conflict between requests to modify a shared cache line Grant 6,763,434 - Arimilli , et al. July 13, 2	2004-07-13
Super-coherent multiprocessor system bus protocols Grant 6,763,435 - Arimilli , et al. July 13, 2	2004-07-13
Method and system for prefetching utilizing memory initiated prefetch write operations Grant 6,760,817 - Arimilli , et al. July 6, 2	2004-07-06
Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory Grant 6,760,809 - Arimilli , et al. July 6, 2	2004-07-06
Decentralized global coherency management in a multi-node computer system Grant 6,754,782 - Arimilli , et al. June 22, 2	2004-06-22
Apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme App 20040117583 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Data processing system having no system memory App 20040117591 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system App 20040117510 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Interrupt mechanism for a data processing system having hardware managed paging of disk data App 20040117589 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Method, processing unit and data processing system for microprocessor communication in a multi-processor system App 20040117603 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Hardware managed virtual-to-physical address translation mechanism App 20040117587 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Access request for a data processing system having no system memory App 20040117588 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Method and data processing system for microprocessor communication in a cluster-based multi-processor system App 20040117511 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network App 20040117598 - Arimilli, Ravi Kumar ; et al.	2004-06-17
Aliasing support for a data processing system having no system memory App 20040117590 - Arimilli, Ravi Kumar ; et al.	2004-06-17
High speed memory cloning facility via a lockless multiprocessor mechanism App 20040111547 - Arimilli, Ravi Kumar ; et al.	2004-06-10
High speed memory cloning facility via a coherently done mechanism App 20040111569 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Dynamic software accessibility to a microprocessor system with a high speed memory cloner App 20040111584 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Interrupt handler prediction method and system App 20040111593 - Arimilli, Ravi Kumar ; et al.	2004-06-10
High speed memory cloning facility via a source/destination switching mechanism App 20040111576 - Arimilli, Ravi Kumar ; et al.	2004-06-10
High speed memory cloner within a data processing system App 20040111577 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Cross partition sharing of state information App 20040111552 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Managing processor architected state upon an interrupt App 20040111572 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states App 20040111591 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Imprecise cache line protection mechanism during a memory clone operation App 20040111581 - Arimilli, Ravi Kumar ; et al.	2004-06-10
High speed memory cloner with extended cache coherency protocols and responses App 20040111565 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Data processing system with naked cache line write operations App 20040111570 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Processor virtualization mechanism via an enhanced restoration of hard architected states App 20040111548 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Dynamically managing saved processor soft states App 20040111562 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Dynamic data routing mechanism for a high speed memory cloner App 20040111575 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/ systems App 20040111653 - Arimilli, Ravi Kumar ; et al.	2004-06-10
Microprocessor reservation mechanism for a hashed address system Grant 6,748,501 - Arimilli , et al. June 8, 2	2004-06-08
Multi-level multiprocessor speculation mechanism Grant 6,748,518 - Guthrie , et al. June 8, 2	2004-06-08
System and method for providing multiprocessor speculation within a speculative branch path Grant 6,728,873 - Guthrie , et al. April 27, 2	2004-04-27
Apparatus for connecting circuit modules Grant 6,725,304 - Arimilli , et al. April 20, 2	2004-04-20
Mechanism for folding storage barrier operations in a multiprocessor system Grant 6,725,340 - Guthrie , et al. April 20, 2	2004-04-20
Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system App 20040073766 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method and system of managing virtualized physical memory in a data processing system App 20040073742 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction App 20040073757 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method, apparatus and system for managing released promotion bits App 20040073756 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method, apparatus and system that cache promotion information within a processor separate from instructions and data App 20040073760 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method and system of managing virtualized physical memory in a memory controller and processor system App 20040073765 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method, apparatus and system for acquiring a global promotion facitily utilizing a data-less transaction App 20040073759 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method and system of managing virtualized physical memory in a multi-processor system App 20040073743 - Arimilli, Ravi Kumar ; et al.	2004-04-15
High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system App 20040073909 - Arimilli, Ravi Kumar ; et al.	2004-04-15
Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction App 20040073734 - Arimilli, Ravi Kumar ; et al.	2004-04-15
High performance data processing system via cache victimization protocols Grant 6,721,853 - Guthrie , et al. April 13, 2	2004-04-13
Local invalidation buses for a highly scalable shared cache memory hierarchy App 20040059871 - Arimilli, Ravi Kumar ; et al.	2004-03-25
Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data Grant 6,711,652 - Arimilli , et al. March 23, 2	2004-03-23
Selectable interface for interfacing integrated circuit modules Grant 6,703,866 - Arimilli , et al. March 9, 2	2004-03-09
Dynamic hardware and software performance optimizations for super-coherent SMP systems Grant 6,704,844 - Arimilli , et al. March 9, 2	2004-03-09
Cache coherency protocol with tagged intervention of modified values Grant 6,701,416 - Arimilli , et al. March 2, 2	2004-03-02
Asynchronous non-blocking snoop invalidation App 20040030843 - Arimilli, Ravi Kumar ; et al.	2004-02-12
Cache invalidation bus for a highly scalable shared cache memory hierarchy App 20040030833 - Arimilli, Ravi Kumar ; et al.	2004-02-12
Multiprocessor speculation mechanism via a barrier speculation flag Grant 6,691,220 - Guthrie , et al. February 10, 2	2004-02-10
Data processing system and method of communication that reduce latency of write transactions subject to retry Grant 6,687,795 - Arimilli , et al. February 3, 2	2004-02-03
Method and apparatus for allocating data usages within an embedded dynamic random access memory device Grant 6,678,814 - Arimilli , et al. January 13, 2	2004-01-13
Dram with memory independent burst lengths for reads versus writes Grant 6,675,270 - Arimilli , et al. January 6, 2	2004-01-06
Multi-node data processing system having a non-hierarchical interconnect architecture Grant 6,671,712 - Arimilli , et al. December 30, 2	2003-12-30
Globally distributed scan blocks Grant 6,665,828 - Arimilli , et al. December 16, 2	2003-12-16
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache Grant 6,662,275 - Arimilli , et al. December 9, 2	2003-12-09
Fixed bus tags for SMP buses Grant 6,662,216 - Arimilli , et al. December 9, 2	2003-12-09
Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control Grant 6,658,538 - Arimilli , et al. December 2, 2	2003-12-02
Super-coherent data mechanisms for shared caches in a multiprocessing system Grant 6,658,539 - Arimilli , et al. December 2, 2	2003-12-02
Cache-coherency protocol with recently read state for extending cache horizontally Grant 6,658,536 - Arimilli , et al. December 2, 2	2003-12-02
Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction Grant 6,658,556 - Arimilli , et al. December 2, 2	2003-12-02
Non-uniform memory access (NUMA) computer system having distributed global coherency management Grant 6,654,857 - Arimilli , et al. November 25, 2	2003-11-25
Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data Grant 6,633,959 - Arimilli , et al. October 14, 2	2003-10-14
Method and apparatus for servicing a processing system through a test port Grant 6,629,268 - Arimilli , et al. September 30, 2	2003-09-30
High speed lock acquisition mechanism with time parameterized cache coherency states Grant 6,629,212 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a persistent "lock acquired" state Grant 6,629,214 - Arimilli , et al. September 30, 2	2003-09-30
Cache coherency protocol permitting sharing of a locked data granule Grant 6,629,209 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a modified store instruction lock release indicator Grant 6,625,701 - Arimilli , et al. September 23, 2	2003-09-23
Multiprocessor speculation mechanism for efficiently managing multiple barrier operations Grant 6,625,660 - Guthrie , et al. September 23, 2	2003-09-23
Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations Grant 6,622,222 - Arimilli , et al. September 16, 2	2003-09-16
Two-stage request protocol for accessing remote memory data in a NUMA data processing system Grant 6,615,322 - Arimilli , et al. September 2, 2	2003-09-02
Store collapsing mechanism for SMP computer system Grant 6,615,320 - Arimilli , et al. September 2, 2	2003-09-02
Mechanism for collapsing store misses in an SMP computer system Grant 6,615,321 - Arimilli , et al. September 2, 2	2003-09-02
System and method for asynchronously overlapping storage barrier operations with old and new storage operations Grant 6,609,192 - Guthrie , et al. August 19, 2	2003-08-19
Method and apparatus for accessing banked embedded dynamic random access memory devices Grant 6,606,680 - Arimilli , et al. August 12, 2	2003-08-12
Multiprocessor speculation mechanism with imprecise recycling of storage operations Grant 6,606,702 - Guthrie , et al. August 12, 2	2003-08-12
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls Grant 6,601,145 - Arimilli , et al. July 29, 2	2003-07-29
Data processing system with HSA (hashed storage architecture) Grant 6,598,118 - Arimilli , et al. July 22, 2	2003-07-22
Multiprocessor system bus protocol with group addresses, responses, and priorities Grant 6,591,321 - Arimilli , et al. July 8, 2	2003-07-08
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response Grant 6,591,307 - Arimilli , et al. July 8, 2	2003-07-08
Scarfing within a hierarchical memory architecture Grant 6,587,924 - Arimilli , et al. July 1, 2	2003-07-01
Elimination of vertical bus queueing within a hierarchical memory architecture Grant 6,587,925 - Arimilli , et al. July 1, 2	2003-07-01
Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system Grant 6,581,116 - Arimilli , et al. June 17, 2	2003-06-17
Multiprocessor computer system with sectored cache line mechanism for cache intervention Grant 6,571,322 - Arimilli , et al. May 27, 2	2003-05-27
Super-coherent multiprocessor system bus protocols App 20030097530 - Arimilli, Ravi Kumar ; et al.	2003-05-22
Super-coherent data mechanisms for shared caches in a multiprocessing system App 20030097528 - Arimilli, Ravi Kumar ; et al.	2003-05-22
High performance symmetric multiprocessing systems via super-coherent data mechanisms App 20030097529 - Arimilli, Ravi Kumar ; et al.	2003-05-22
Dynamic hardware and software performance optimizations for super-coherent SMP systems App 20030097531 - Arimilli, Ravi Kumar ; et al.	2003-05-22
Symmetric multiprocessor systems with an independent super-coherent cache directory App 20030093624 - Arimilli, Ravi Kumar ; et al.	2003-05-15
Bus master for SMP execution of global operations utilizing a single token with implied release Grant 6,553,442 - Arimilli , et al. April 22, 2	2003-04-22
Extended cache coherency protocol with a "lock released" state Grant 6,549,989 - Arimilli , et al. April 15, 2	2003-04-15
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update Grant 6,546,468 - Arimilli , et al. April 8, 2	2003-04-08
Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations Grant 6,535,939 - Arimilli , et al. March 18, 2	2003-03-18
Data processing system and method with dynamic idle for tunable interface calibration App 20030046596 - Floyd, Michael Stephen ; et al.	2003-03-06
Robust system bus recovery App 20030033555 - Joyner, Jody Bern ; et al.	2003-02-13
Method and apparatus for transmitting packets within a symmetric multiprocessor system App 20030033350 - Arimilli, Ravi Kumar ; et al.	2003-02-13
Multi-node data processing system and communication protocol having a partial combined response Grant 6,519,649 - Arimilli , et al. February 11, 2	2003-02-11
Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism App 20030023782 - Arimilli, Ravi Kumar ; et al.	2003-01-30
DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism App 20030023783 - Arimilli, Ravi Kumar ; et al.	2003-01-30
Elimination of vertical bus queueing within a hierarchical memory architecture App 20030014592 - Arimilli, Ravi Kumar ; et al.	2003-01-16
Method And Apparatus For Concurrently Communicating With Multiple Embedded Dynamic Random Access Memory Devices App 20030014606 - Arimilli, Ravi Kumar ; et al.	2003-01-16
Incremental tag build for hierarchical memory architecture App 20030014593 - Arimilli, Ravi Kumar ; et al.	2003-01-16
Scarfing within a hierarchical memory architecture App 20030014591 - Arimilli, Ravi Kumar ; et al.	2003-01-16
Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens Grant 6,507,880 - Arimilli , et al. January 14, 2	2003-01-14
Non-uniform memory access (NUMA) computer system having distributed global coherency management App 20030009635 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Method and system for prefetching utilizing memory initiated prefetch write operations App 20030009632 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data App 20030009634 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control App 20030009640 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Two-stage request protocol for accessing remote memory data in a NUMA data processing system App 20030009643 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Memory directory management in a multi-node computer system App 20030009631 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data App 20030009639 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory App 20030009623 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Decentralized global coherency management in a multi-node computer system App 20030009637 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (numa) computer system App 20030009641 - Arimilli, Ravi Kumar ; et al.	2003-01-09
Method for just-in-time delivery of load data by intervening caches Grant 6,505,277 - Arimilli , et al. January 7, 2	2003-01-07
Method and apparatus for accessing banked embedded dynamic random access momory devices App 20030005211 - Arimilli, Ravi Kumar ; et al.	2003-01-02
Imprecise snooping based invalidation mechanism App 20030005236 - Arimilli, Ravi Kumar ; et al.	2003-01-02
Method and apparatus for allocating data usages within an embedded dynamic random access memory device App 20030005215 - Arimilli, Ravi Kumar ; et al.	2003-01-02
High performance data processing system via cache victimization protocols App 20030005232 - Guthrie, Guy Lynn ; et al.	2003-01-02
Cache having virtual cache controller queues Grant 6,502,168 - Arimilli , et al. December 31, 2	2002-12-31
Method and system for clearing dependent speculations from a request queue Grant 6,487,637 - Arimilli , et al. November 26, 2	2002-11-26
ECC mechanism for set associative cache array Grant 6,480,975 - Arimilli , et al. November 12, 2	2002-11-12
Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release Grant 6,480,915 - Arimilli , et al. November 12, 2	2002-11-12
Cache index based system address bus Grant 6,477,613 - Arimilli , et al. November 5, 2	2002-11-05
Dram with memory independent burst lengths for reads versus writes App 20020161966 - Arimilli, Ravi Kumar ; et al.	2002-10-31
Speculative dram reads with cancel data mechanism App 20020161979 - Arimilli, Ravi Kumar ; et al.	2002-10-31
Processor assigning data to hardware partition based on selectable hash of data address Grant 6,470,442 - Arimilli , et al. October 22, 2	2002-10-22
Programmable agent and method for managing prefetch queues Grant 6,470,427 - Arimilli , et al. October 22, 2	2002-10-22
Communication method for integrated circuit chips on a multi-chip module Grant 6,463,497 - Arimilli , et al. October 8, 2	2002-10-08
Layered local cache with lower level cache updating upper and lower level cache directories Grant 6,463,507 - Arimilli , et al. October 8, 2	2002-10-08
Data processing system and method for resolving a conflict between requests to modify a shared cache line App 20020129211 - Arimilli, Ravi Kumar ; et al.	2002-09-12
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers App 20020129209 - Arimilli, Ravi Kumar ; et al.	2002-09-12
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls App 20020129210 - Arimilli, Ravi Kumar ; et al.	2002-09-12
Data processing system and method of communication that reduce latency of write transactions subject to retry App 20020124145 - Arimilli, Ravi Kumar ; et al.	2002-09-05
Method for upper level cache victim selection management by a lower level cache Grant 6,446,166 - Arimilli , et al. September 3, 2	2002-09-03
Method and system for cancelling speculative cache prefetch requests Grant 6,438,656 - Arimilli , et al. August 20, 2	2002-08-20
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache App 20020112124 - Arimilli, Ravi Kumar ; et al.	2002-08-15
Mechanism for collapsing store misses in an SMP computer system App 20020112128 - Arimilli, Ravi Kumar ; et al.	2002-08-15
Store collapsing mechanism for SMP computer system App 20020112130 - Arimilli, Ravi Kumar ; et al.	2002-08-15
Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache App 20020112129 - Arimilli, Ravi Kumar ; et al.	2002-08-15
Method of cache management to dynamically update information-type dependent cache policies Grant 6,434,669 - Arimilli , et al. August 13, 2	2002-08-13
Method of cache management to store information in particular regions of the cache according to information-type Grant 6,434,668 - Arimilli , et al. August 13, 2	2002-08-13
Cache management mechanism to enable information-type dependent cache policies Grant 6,425,058 - Arimilli , et al. July 23, 2	2002-07-23
Partitioned cache and management method for selectively caching data by type Grant 6,421,761 - Arimilli , et al. July 16, 2	2002-07-16
Method and system for managing speculative requests in a multi-level memory hierarchy Grant 6,418,516 - Arimilli , et al. July 9, 2	2002-07-09
Removal of posted operations from cache operations queue Grant 6,418,514 - Arimilli , et al. July 9, 2	2002-07-09
Multiprocessor computer system with sectored cache line mechanism for cache intervention App 20020087809 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Multiprocessor computer system with sectored cache line mechanism for load and store operations App 20020087792 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors App 20020087828 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Microprocessor reservation mechanism for a hashed address system App 20020087815 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Full multiprocessor speculation mechanism in a symmetric multiprocessor (smp) System App 20020087849 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Multiprocessor computer system with sectored cache line system bus protocol mechanism App 20020087791 - Arimilli, Ravi Kumar ; et al.	2002-07-04
Multiprocessor system with a high performance integrated distributed switch (IDS) controller Grant 6,415,424 - Arimilli , et al. July 2, 2	2002-07-02
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update App 20020083268 - Arimilli, Ravi Kumar ; et al.	2002-06-27
Apparatus for associating cache memories with processors within a multiprocessor data processing system App 20020078309 - Arimilli, Ravi Kumar ; et al.	2002-06-20
Apparatus for connecting circuit modules App 20020078280 - Arimilli, Ravi Kumar ; et al.	2002-06-20
Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data Grant 6,408,362 - Arimilli , et al. June 18, 2	2002-06-18
Multiprocessor system bus protocol for O state memory-consistent data Grant 6,405,290 - Arimilli , et al. June 11, 2	2002-06-11
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response Grant 6,405,289 - Arimilli , et al. June 11, 2	2002-06-11
Layered local cache mechanism with split register load bus and cache load bus Grant 6,405,285 - Arimilli , et al. June 11, 2	2002-06-11
High performance store instruction management via imprecise local cache update mechanism Grant 6,397,300 - Arimilli , et al. May 28, 2	2002-05-28
Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines Grant 6,397,303 - Arimilli , et al. May 28, 2	2002-05-28
Cache memory having a programmable cache replacement scheme Grant 6,397,298 - Arimilli , et al. May 28, 2	2002-05-28
Optimized cache allocation algorithm for multiple speculative requests Grant 6,393,528 - Arimilli , et al. May 21, 2	2002-05-21
Cache-coherency protocol with upstream undefined state Grant 6,374,330 - Arimilli , et al. April 16, 2	2002-04-16
Method and system for allocating lower level cache entries for data castout from an upper level cache Grant 6,370,618 - Arimilli , et al. April 9, 2	2002-04-09
Extended cache state with prefetched stream ID information Grant 6,360,299 - Arimilli , et al. March 19, 2	2002-03-19
Method and system for bypassing cache levels when casting out from an upper level cache Grant 6,356,980 - Arimilli , et al. March 12, 2	2002-03-12
High performance mechanism to support O state horizontal cache-to-cache transfers Grant 6,349,368 - Arimilli , et al. February 19, 2	2002-02-19
Method and system for communication in which a castout operation is cancelled in response to snoop responses Grant 6,349,367 - Arimilli , et al. February 19, 2	2002-02-19
Cache coherency protocols with posted operations Grant 6,347,361 - Arimilli , et al. February 12, 2	2002-02-12
Method of cache management for dynamically disabling O state memory-consistent data Grant 6,345,341 - Arimilli , et al. February 5, 2	2002-02-05
Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Grant 6,345,342 - Arimilli , et al. February 5, 2	2002-02-05
System bus directory snooping mechanism for read/castout (RCO) address transaction Grant 6,343,344 - Arimilli , et al. January 29, 2	2002-01-29
Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction Grant 6,343,347 - Arimilli , et al. January 29, 2	2002-01-29
Cache coherency protocol having tagged state used with cross-bars Grant 6,341,336 - Arimilli , et al. January 22, 2	2002-01-22
Cache coherency protocols with global and local posted operations Grant 6,330,643 - Arimilli , et al. December 11, 2	2001-12-11
High performance multiprocessor system with modified-unsolicited cache state Grant 6,321,306 - Arimilli , et al. November 20, 2	2001-11-20
Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data Grant 6,321,305 - Arimilli , et al. November 20, 2	2001-11-20
Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations Grant 6,314,495 - Arimilli , et al. November 6, 2	2001-11-06
Queued arbitration mechanism for data processing system Grant 6,286,068 - Arimilli , et al. September 4, 2	2001-09-04
Multiprocessor system bus with a data-less castout mechanism Grant 6,282,615 - Arimilli , et al. August 28, 2	2001-08-28
Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position Grant 6,279,086 - Arimilli , et al. August 21, 2	2001-08-21
Cache coherency protocol including an HR state Grant 6,275,908 - Arimilli , et al. August 14, 2	2001-08-14
Multiprocessor system bus with system controller explicitly updating snooper cache state information Grant 6,275,909 - Arimilli , et al. August 14, 2	2001-08-14
Cache coherency protocol having hovering (H), recent (R), and tagged (T) states Grant 6,272,603 - Arimilli , et al. August 7, 2	2001-08-07
Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode Grant 6,263,407 - Arimilli , et al. July 17, 2	2001-07-17
Cache coherency protocol with selectively implemented tagged state Grant 6,247,098 - Arimilli , et al. June 12, 2	2001-06-12
Eviction override for larx-reserved addresses Grant 6,212,605 - Arimilli , et al. April 3, 2	2001-04-03
Deallocation with cache update protocol (L2 evictions) Grant 6,195,729 - Arimilli , et al. February 27, 2	2001-02-27
High performance cache directory addressing scheme for variable cache sizes utilizing associativity Grant 6,192,458 - Arimilli , et al. February 20, 2	2001-02-20
Cache coherency protocol for a data processing system including a multi-level memory hierarchy Grant 6,192,451 - Arimilli , et al. February 20, 2	2001-02-20
Demand-based issuance of cache operations to a system bus Grant 6,182,201 - Arimilli , et al. January 30, 2	2001-01-30