Arimilli; Lakshminarayana Baba

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arimilli; Lakshminarayana Baba.The latest application filed is for "pre-transmission data reordering for a serial interface".

Company Profile

1.41.8

Arimilli; Lakshminarayana Baba - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Pre-transmission data reordering for a serial interface Grant 10,216,653 - Arimilli , et al. Feb	2019-02-26
Pre-transmission Data Reordering For A Serial Interface App 20180095905 - ARIMILLI; LAKSHMINARAYANA BABA ; et al.	2018-04-05
Techniques for dynamically assigning jobs to processors in a cluster using local job tables Grant 9,396,021 - Arimilli , et al. July 19, 2	2016-07-19
Techniques for dynamically assigning jobs to processors in a cluster based on inter-thread communications Grant 9,384,042 - Arimilli , et al. July 5, 2	2016-07-05
Techniques for cache injection in a processor system based on a shared state Grant 9,336,145 - Arimilli , et al. May 10, 2	2016-05-10
Techniques for cache injection in a processor system from a remote node Grant 9,268,703 - Arimilli , et al. February 23, 2	2016-02-23
Techniques for cache injection in a processor system using a cache injection instruction Grant 9,256,540 - Arimilli , et al. February 9, 2	2016-02-09
Techniques for cache injection in a processor system responsive to a specific instruction sequence Grant 8,443,146 - Arimilli , et al. May 14, 2	2013-05-14
Techniques for cache injection in a processor system with replacement policy position modification Grant 8,429,349 - Arimilli , et al. April 23, 2	2013-04-23
Processor system and methods of triggering a block move using a system bus write command initiated by user code Grant 8,281,075 - Arimilli , et al. October 2, 2	2012-10-02
Techniques for dynamically assigning jobs to processors in a cluster based on processor workload Grant 8,239,524 - Arimilli , et al. August 7, 2	2012-08-07
Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information Grant 8,122,132 - Arimilli , et al. February 21, 2	2012-02-21
Techniques For Cache Injection In A Processor System From A Remote Node App 20100268896 - Arimilli; Lakshminarayana Baba ; et al.	2010-10-21
Techniques For Cache Injection In A Processor System Based On A Shared State App 20100262787 - Arimilli; Lakshminarayana Baba ; et al.	2010-10-14
Techniques For Triggering A Block Move Using A System Bus Write Command Initiated By User Code App 20100262735 - Arimilli; Lakshminarayana Baba ; et al.	2010-10-14
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Using Local Job Tables App 20100153966 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Broadcast Information App 20100153542 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Inter-thread Communications App 20100153965 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Techniques For Dynamically Assigning Jobs To Processors In A Cluster Based On Processor Workload App 20100153541 - Arimilli; Lakshminarayana Baba ; et al.	2010-06-17
Multi-state logic analyzer integral to a microprocessor Grant 6,633,838 - Arimilli , et al. October 14, 2	2003-10-14
High speed lock acquisition mechanism with time parameterized cache coherency states Grant 6,629,212 - Arimilli , et al. September 30, 2	2003-09-30
Cache coherency protocol permitting sharing of a locked data granule Grant 6,629,209 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a persistent "lock acquired" state Grant 6,629,214 - Arimilli , et al. September 30, 2	2003-09-30
Extended cache coherency protocol with a modified store instruction lock release indicator Grant 6,625,701 - Arimilli , et al. September 23, 2	2003-09-23
Extended cache coherency protocol with a "lock released" state Grant 6,549,989 - Arimilli , et al. April 15, 2	2003-04-15
Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations Grant 6,535,939 - Arimilli , et al. March 18, 2	2003-03-18
Method for just-in-time delivery of load data by intervening caches Grant 6,505,277 - Arimilli , et al. January 7, 2	2003-01-07
Method of cache management to store information in particular regions of the cache according to information-type Grant 6,434,668 - Arimilli , et al. August 13, 2	2002-08-13
Method of cache management to dynamically update information-type dependent cache policies Grant 6,434,669 - Arimilli , et al. August 13, 2	2002-08-13
Cache management mechanism to enable information-type dependent cache policies Grant 6,425,058 - Arimilli , et al. July 23, 2	2002-07-23
Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data Grant 6,408,362 - Arimilli , et al. June 18, 2	2002-06-18
Multiprocessor system bus protocol for O state memory-consistent data Grant 6,405,290 - Arimilli , et al. June 11, 2	2002-06-11
Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines Grant 6,397,303 - Arimilli , et al. May 28, 2	2002-05-28
Optimized cache allocation algorithm for multiple speculative requests Grant 6,393,528 - Arimilli , et al. May 21, 2	2002-05-21
Method and system for allocating lower level cache entries for data castout from an upper level cache Grant 6,370,618 - Arimilli , et al. April 9, 2	2002-04-09
Extended cache state with prefetched stream ID information Grant 6,360,299 - Arimilli , et al. March 19, 2	2002-03-19
Method and system for bypassing cache levels when casting out from an upper level cache Grant 6,356,980 - Arimilli , et al. March 12, 2	2002-03-12
High performance mechanism to support O state horizontal cache-to-cache transfers Grant 6,349,368 - Arimilli , et al. February 19, 2	2002-02-19
Method of cache management for dynamically disabling O state memory-consistent data Grant 6,345,341 - Arimilli , et al. February 5, 2	2002-02-05
Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Grant 6,345,342 - Arimilli , et al. February 5, 2	2002-02-05
High performance multiprocessor system with modified-unsolicited cache state Grant 6,321,306 - Arimilli , et al. November 20, 2	2001-11-20
Multiprocessor system bus with a data-less castout mechanism Grant 6,282,615 - Arimilli , et al. August 28, 2	2001-08-28

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