Arayama; Masashi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Arayama; Masashi.The latest application filed is for "circuit delay analyzing apparatus, circuit delay analyzing method, and non-transitory computer-readable recording medium".

Company Profile

0.8.12

Arayama; Masashi - Gamagori JP
Arayama; Masashi - Kawasaki JP
Arayama; Masashi - Yokohama JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit Delay Analyzing Apparatus, Circuit Delay Analyzing Method, And Non-transitory Computer-readable Recording Medium App 20180210988 - Arayama; Masashi	2018-07-26
Design Support Device, Design Support Method, And Computer-readable Recording Medium Having Stored Therein Design Support Program App 20140337657 - Watanabe; Yuuki ; et al.	2014-11-13
Support Device, Design Support Method, And Computer-readable Recording Medium App 20140317586 - Makino; Sumiko ; et al.	2014-10-23
Layout Design Apparatus And Layout Design Method App 20140157220 - Arayama; Masashi ; et al.	2014-06-05
Layout design apparatus and layout design method Grant 8,689,167 - Arayama , et al. April 1, 2	2014-04-01
Macro layout verification appartus Grant 8,539,412 - Arayama , et al. September 17, 2	2013-09-17
Layout Design Apparatus And Layout Design Method App 20130036396 - Arayama; Masashi ; et al.	2013-02-07
Macro Layout Verification Appartus App 20130014067 - Arayama; Masashi ; et al.	2013-01-10
Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout Grant 8,286,117 - Arayama , et al. October 9, 2	2012-10-09
Delay Library Generation Device And Method App 20110302548 - ARAYAMA; Masashi	2011-12-08
Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof Grant 8,000,951 - Arayama August 16, 2	2011-08-16
Macro Layout Verification Apparatus App 20100235797 - ARAYAMA; Masashi ; et al.	2010-09-16
Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence Grant 7,739,638 - Arayama June 15, 2	2010-06-15
Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof App 20080154571 - Arayama; Masashi	2008-06-26
Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium App 20050155005 - Arayama, Masashi	2005-07-14
Activation path simulation equipment and activation path simulation method Grant 6,434,728 - Arayama , et al. August 13, 2	2002-08-13

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