Appaswamy; Aravind Chennimalai
Patent Applications and Registrations
Patent applications and USPTO patent grants for Appaswamy; Aravind Chennimalai.The latest application filed is for "integrated guard structure for controlling conductivity modulation in diodes".
- Appaswamy; Aravind Chennimalai - Plano TX
| Patent | Date |
|---|---|
| Compact Area Electrostatic Discharge Protection Circuit App 20220223580 - DiSarro; James Paul ; et al. | 2022-07-14 |
| Lateral High Voltage Scr With Integrated Negative Strike Diode App 20220223584 - Appaswamy; Aravind Chennimalai | 2022-07-14 |
| Integrated Guard Structure For Controlling Conductivity Modulation In Diodes App 20220223683 - Appaswamy; Aravind Chennimalai | 2022-07-14 |
| ESD protection circuit with passive trigger voltage controlled shut-off Grant 10,749,336 - Mysore Rajagopal , et al. A | 2020-08-18 |
| IGBT coupled to a reverse bias device in series Grant 10,249,610 - Appaswamy , et al. | 2019-04-02 |
| Esd Protection Circuit With Passive Trigger Voltage Controlled Shut-off App 20180152019 - Mysore Rajagopal; Krishna Praveen ; et al. | 2018-05-31 |
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