| Patent | Date |
|---|
Phase-locked loop circuit, information processing apparatus, and information processing system
Grant 6,947,514 - Kato , et al. September 20, 2 | 2005-09-20 |
Semiconductor integrated circuit having oscillators or oscillation circuits connected to a wiring line at connection points with intervals in length there between
Grant 6,922,113 - Mizuno , et al. July 26, 2 | 2005-07-26 |
Semiconductor integrated circuit device
Grant 6,879,188 - Miyazaki , et al. April 12, 2 | 2005-04-12 |
Semiconductor integrated circuit having oscillators or oscillation circuits connected to a wiring line at connection points with intervals in length therebetween
App 20040100333 - Mizuno, Hiroyuki ; et al. | 2004-05-27 |
Semiconductor integrated circuit having oscillators or oscillation circuits connected to a wiring line at connection points with intervals in length therebetween
Grant 6,683,503 - Mizuno , et al. January 27, 2 | 2004-01-27 |
Semiconductor integrated circuit device
App 20030098730 - Miyazaki, Masayuki ; et al. | 2003-05-29 |
Semiconductor integrated circuit device
Grant 6,515,519 - Miyazaki , et al. February 4, 2 | 2003-02-04 |
Timing-control circuit device and clock distribution system
Grant 6,489,824 - Miyazaki , et al. December 3, 2 | 2002-12-03 |
Semiconductor Integrated Circuit Having Oscillators Or Oscillation Circuits Connected To A Wiring Line At Connection Points With Intervals In Length Therebetween
App 20020003452 - MIZUNO, HIROYUKI ; et al. | 2002-01-10 |
Timing-control circuit device and clock distribution system
App 20020000851 - Miyazaki, Masayuki ; et al. | 2002-01-03 |
Multi-processor system for invalidating hierarchical cache
Grant 5,287,484 - Nishii , et al. February 15, 1 | 1994-02-15 |
Multiprocessor cache system having three states for generating invalidating signals upon write accesses
Grant 5,283,886 - Nishii , et al. February 1, 1 | 1994-02-01 |
Static memory containing sense amp and sense amp switching circuit
Grant 5,267,198 - Hatano , et al. November 30, 1 | 1993-11-30 |
Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
Grant 5,202,969 - Sato , et al. April 13, 1 | 1993-04-13 |
Static memory containing sense AMP and sense AMP switching circuit
Grant 5,193,075 - Hatano , et al. March 9, 1 | 1993-03-09 |
Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register
Grant 5,146,573 - Sato , et al. September 8, 1 | 1992-09-08 |
Multi-processing system and cache apparatus for use in the same
Grant 5,140,681 - Uchiyama , et al. August 18, 1 | 1992-08-18 |
Microprocessor which terminates bus cycle when access address falls within a predetermined processor system address space
Grant 5,109,492 - Noguchi , et al. April 28, 1 | 1992-04-28 |
Content-addressed memory
Grant 4,831,586 - Nakagawa , et al. May 16, 1 | 1989-05-16 |
Address translation unit
Grant 4,812,969 - Takagi , et al. March 14, 1 | 1989-03-14 |
Series resonance drive circuit for magnetic bubble memory
Grant 4,379,341 - Toyooka , et al. April 5, 1 | 1983-04-05 |
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