Ang; Chew Hoe

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ang; Chew Hoe.The latest application filed is for "method for forming high-k charge storage device".

Company Profile

0.25.25

Ang; Chew Hoe - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for monitoring endcap pullback Grant 7,795,046 - Dakshina-Murthy , et al. September 14, 2	2010-09-14
Test structure for automatic dynamic negative-bias temperature instability testing Grant 7,562,318 - Ang , et al. July 14, 2	2009-07-14
Method For Forming High-k Charge Storage Device App 20090023280 - ANG; Chew-Hoe ; et al.	2009-01-22
Method for forming high-K charge storage device Grant 7,479,425 - Ang , et al. January 20, 2	2009-01-20
Method and Apparatus for Monitoring Endcap Pullback App 20080283878 - Dakshina-Murthy; Srikanteswara ; et al.	2008-11-20
Semiconductor Device With Doped Transistor App 20080087958 - Verma; Purakh Raj ; et al.	2008-04-17
Semiconductor device and fabrication method Grant 7,326,609 - Verma , et al. February 5, 2	2008-02-05
Integrated Circuit Stress Control System App 20070090484 - Lee; Jae Gon ; et al.	2007-04-26
Method to fabricate Ge and Si devices together for performance enhancement Grant 7,202,140 - Ang , et al. April 10, 2	2007-04-10
Ultra-thin gate oxide through post decoupled plasma nitridation anneal Grant 7,176,094 - Zhong , et al. February 13, 2	2007-02-13
Novel Test Structure For Automatic Dynamic Negative-bias Temperature Instability Testing App 20060282804 - Ang; Chew Hoe ; et al.	2006-12-14
Semiconductor Device And Fabrication Method App 20060252188 - Verma; Purakh Raj ; et al.	2006-11-09
Charge pump current source Grant 7,132,878 - Chen , et al. November 7, 2	2006-11-07
Test structure for automatic dynamic negative-bias temperature instability testing Grant 7,103,861 - Ang , et al. September 5, 2	2006-09-05
High K artificial lattices for capacitor applications to use in Cu or Al BEOL Grant 7,095,073 - Balakumar , et al. August 22, 2	2006-08-22
Method for forming high-K charge storage device App 20060160303 - Ang; Chew-Hoe ; et al.	2006-07-20
Method for engineering hybrid orientation/material semiconductor substrate App 20060105533 - Chong; Yung Fu ; et al.	2006-05-18
Charge pump current source App 20060103450 - Chen; Tupei ; et al.	2006-05-18
Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration Grant 7,022,625 - Ang , et al. April 4, 2	2006-04-04
Novel test structure for automatic dynamic negative-bias temperature instability testing App 20050278677 - Ang, Chew Hoe ; et al.	2005-12-15
High K artificial lattices for capacitor applications to use in Cu or Al BEOL App 20050118780 - Balakumar, Subramanian ; et al.	2005-06-02
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20050101083 - Ang, Chew Hoe ; et al.	2005-05-12
Method to pattern small features by using a re-flowable hard mask App 20050089777 - Ang, Chew-Hoe ; et al.	2005-04-28
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing Grant 6,841,441 - Ang , et al. January 11, 2	2005-01-11
Formation of small gates beyond lithographic limits App 20040266155 - Ang, Chew Hoe ; et al.	2004-12-30
High K artificial lattices for capacitor applications to use in CU or AL BEOL Grant 6,830,971 - Balakumar , et al. December 14, 2	2004-12-14
Method to pattern small features by using a re-flowable hard mask Grant 6,828,082 - Ang , et al. December 7, 2	2004-12-07
Method of forming a high performance and low cost CMOS device Grant 6,762,085 - Zheng , et al. July 13, 2	2004-07-13
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20040132271 - Ang, Chew Hoe ; et al.	2004-07-08
Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth Grant 6,743,291 - Ang , et al. June 1, 2	2004-06-01
Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape Grant 6,734,082 - Zheng , et al. May 11, 2	2004-05-11
High K artificial lattices for capacitor applications to use in CU or AL BEOL App 20040087101 - Balakumar, Subramanian ; et al.	2004-05-06
Method of forming a high performance and low cost CMOS device App 20040063264 - Zheng, Jia Zhen ; et al.	2004-04-01
Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization Grant 6,709,912 - Ang , et al. March 23, 2	2004-03-23
Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape App 20040029353 - Zheng, Jia Zhen ; et al.	2004-02-12
Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknesses App 20040029321 - Ang, Chew Hoe ; et al.	2004-02-12
Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration App 20040018674 - Ang, Chew Hoe ; et al.	2004-01-29
Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth App 20040007170 - Ang, Chew Hoe ; et al.	2004-01-15
Triple gate oxide process with high-k gate dielectric Grant 6,670,248 - Ang , et al. December 30, 2	2003-12-30
Method for forming L-shaped spacers with precise width control Grant 6,664,156 - Ang , et al. December 16, 2	2003-12-16
Method to fabricate a single gate with dual work-functions Grant 6,664,153 - Ang , et al. December 16, 2	2003-12-16
Method of fabricating variable length vertical transistors Grant 6,632,712 - Ang , et al. October 14, 2	2003-10-14
Ultra-thin gate oxide through post decoupled plasma nitridation anneal App 20030170956 - Zhong, Dong ; et al.	2003-09-11
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask Grant 6,610,604 - Ang , et al. August 26, 2	2003-08-26
Forming dual gate oxide thickness on vertical transistors by ion implantation Grant 6,610,575 - Ang , et al. August 26, 2	2003-08-26
Method to fabricate a single gate with dual work-functions App 20030153139 - Ang, Chew Hoe ; et al.	2003-08-14
Method to pattern small features by using a re-flowable hard mask App 20030152871 - Ang, Chew-Hoe ; et al.	2003-08-14
Method of fabricating CMOS device with dual gate electrode Grant 6,605,501 - Ang , et al. August 12, 2	2003-08-12
Method Of Forming Small Transistor Gates By Using Self-aligned Reverse Spacer As A Hard Mask App 20030148617 - Ang, Chew-Hoe ; et al.	2003-08-07
Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate Grant 6,429,109 - Zheng , et al. August 6, 2	2002-08-06

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