Ang; Boon Yong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ang; Boon Yong.The latest application filed is for "integrated circuit with mosfet fuse element".

Company Profile

0.19.5

Ang; Boon Yong - Santa Clara CA US
Ang; Boon-Yong - Cupertino CA
Ang; Boon Yong - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit with MOSFET fuse element Grant 8,564,023 - Im , et al. October 22, 2	2013-10-22
Field effect transistor having increased carrier mobility Grant 7,923,785 - Xiang , et al. April 12, 2	2011-04-12
Electronic fuse cell with enhanced thermal gradient Grant 7,923,811 - Im , et al. April 12, 2	2011-04-12
Multi-step programming of E fuse cells Grant 7,834,659 - Im , et al. November 16, 2	2010-11-16
Electronic fuse programming current generator with on-chip reference Grant 7,724,600 - Im , et al. May 25, 2	2010-05-25
Electronic fuse array Grant 7,710,813 - Im , et al. May 4, 2	2010-05-04
CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer Grant 7,688,639 - Paak , et al. March 30, 2	2010-03-30
Integrated circuit with fuse programming damage detection Grant 7,598,749 - Ang , et al. October 6, 2	2009-10-06
Integrated Circuit With Mosfet Fuse Element App 20090224323 - Im; Hsung Jai ; et al.	2009-09-10
One-time-programmable logic bit with multiple logic elements Grant 7,567,449 - Paak , et al. July 28, 2	2009-07-28
Oxygen elimination for device processing Grant 7,381,620 - Ang , et al. June 3, 2	2008-06-03
One-time-programmable logic bit with multiple logic elements App 20080101146 - Paak; Sunhom ; et al.	2008-05-01
Test circuit and method of use thereof for the manufacture of integrated circuits Grant 7,312,625 - Paak , et al. December 25, 2	2007-12-25
CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer Grant 7,294,888 - Paak , et al. November 13, 2	2007-11-13
Bond pad structure for copper metallization having increased reliability and method for fabricating same Grant 7,242,102 - Kang , et al. July 10, 2	2007-07-10
Method for achieving increased control over interconnect line thickness across a wafer and between wafers Grant 7,122,465 - Ang , et al. October 17, 2	2006-10-17
Bond pad structure for copper metallization having increased reliability and method for fabricating same App 20060006552 - Kang; Inkuk ; et al.	2006-01-12
Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing Grant 6,974,989 - Chen , et al. December 13, 2	2005-12-13
Method for integrating a high-k gate dielectric in a transistor fabrication process App 20050101147 - Labelle, Catherine B. ; et al.	2005-05-12
Detecting heat generating failures in unpassivated semiconductor devices Grant 6,866,416 - Mahanpour , et al. March 15, 2	2005-03-15
Field effect transistor having increased carrier mobility App 20050040477 - Xiang, Qi ; et al.	2005-02-24
Method and apparatus for polishing an outer edge ring on a semiconductor wafer Grant 6,824,446 - Ang , et al. November 30, 2	2004-11-30
Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect Grant 6,627,484 - Ang September 30, 2	2003-09-30

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