Ang; Boon Jin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ang; Boon Jin.The latest application filed is for "frequency control clock tuning circuitry".

Company Profile

1.44.9

Ang; Boon Jin - Butterworth MY
Ang; Boon Jin - Penang N/A MY
Ang; Boon Jin - Bagan Ajam Butterworth N/A MY
Ang; Boon Jin - Bagan Ajam N/A MY
Ang; Boon Jin - B'Worth MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit with dynamically-adjustable buffer space for serial interface Grant 10,339,074 - Tan , et al.	2019-07-02
Integrated circuit with dynamically-adjustable buffer space for serial interface Grant 9,680,773 - Tan , et al. June 13, 2	2017-06-13
High speed IO buffer Grant 9,166,591 - Chan , et al. October 20, 2	2015-10-20
Integrated circuit system with dynamic decoupling and method of manufacture thereof Grant 9,153,572 - Oh , et al. October 6, 2	2015-10-06
Method and apparatus for determining clock uncertainties Grant 8,739,099 - Maruri , et al. May 27, 2	2014-05-27
Memory circuitry with dynamic power control Grant 8,699,291 - Ch'ng , et al. April 15, 2	2014-04-15
Predicting routability of integrated circuits Grant 8,694,944 - Soo , et al. April 8, 2	2014-04-08
Integrated circuit with configurable I/O transistor arrangement Grant 8,686,758 - Sia , et al. April 1, 2	2014-04-01
Frequency control clock tuning circuitry Grant 8,659,334 - Lim , et al. February 25, 2	2014-02-25
Memory error detection circuitry Grant 8,612,814 - Tan , et al. December 17, 2	2013-12-17
Multiplier with built-in accumulator Grant 8,533,250 - Foo , et al. September 10, 2	2013-09-10
Configurable memory block Grant 8,400,863 - Tan , et al. March 19, 2	2013-03-19
Frequency Control Clock Tuning Circuitry App 20120274375 - Lim; Teik Wah ; et al.	2012-11-01
Frequency control clock tuning circuitry Grant 8,232,823 - Lim , et al. July 31, 2	2012-07-31
Data encoding scheme to reduce sense current Grant 8,189,362 - Tan , et al. May 29, 2	2012-05-29
Method of designing integrated circuits including providing an option to select a mask layer set Grant 8,151,224 - Ang , et al. April 3, 2	2012-04-03
Data Encoding Scheme To Reduce Sense Current App 20110292711 - Tan; Jun Pin ; et al.	2011-12-01
Techniques for performing built-in self-test of receiver channel having a serializer Grant 8,037,377 - Chia , et al. October 11, 2	2011-10-11
Programmable control of mask-programmable integrated circuit devices Grant 8,037,444 - Ang , et al. October 11, 2	2011-10-11
Data encoding scheme to reduce sense current Grant 7,978,493 - Tan , et al. July 12, 2	2011-07-12
Techniques for optimizing design of a hard intellectual property block for data transmission Grant 7,843,216 - van Wageningen , et al. November 30, 2	2010-11-30
Dynamic real-time delay characterization and configuration Grant 7,787,314 - Tan , et al. August 31, 2	2010-08-31
Delay circuit with delay cells in different orientations Grant 7,683,689 - Lui , et al. March 23, 2	2010-03-23
Dynamic Real-time Delay Characterization And Configuration App 20100061166 - Tan; Jun Pin ; et al.	2010-03-11
Techniques for reducing clock skew in clock routing networks Grant 7,639,047 - Ang , et al. December 29, 2	2009-12-29
Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices Grant 7,565,390 - Lui , et al. July 21, 2	2009-07-21
Techniques for debugging hard intellectual property blocks Grant 7,479,803 - Wageningen , et al. January 20, 2	2009-01-20
Techniques For Optimizing Design Of A Hard Intellectual Property Block For Data Transmission App 20080297192 - van WAGENINGEN; Darren ; et al.	2008-12-04
Techniques for optimizing design of a hard intellectual property block for data transmission Grant 7,434,192 - van Wageningen , et al. October 7, 2	2008-10-07
Method for transferring data across different clock domains with selectable delay Grant 7,363,526 - Chong , et al. April 22, 2	2008-04-22
Programmable soft macro memory using gate array base cells Grant 7,305,640 - Phoon , et al. December 4, 2	2007-12-04
LVDS output buffer pre-emphasis methods and apparatus Grant 7,265,587 - Ng , et al. September 4, 2	2007-09-04
Techniques for combining volatile and non-volatile programmable logic on an integrated circuit Grant 7,242,218 - Camarota , et al. July 10, 2	2007-07-10
Signal propagation circuitry for use on integrated circuits Grant 7,233,189 - Ang , et al. June 19, 2	2007-06-19
Techniques for implementing hardwired decoders in differential input circuits Grant 7,218,141 - Ng , et al. May 15, 2	2007-05-15
Techniques for optimizing design of a hard intellectual property block for data transmission App 20060125517 - van Wageningen; Darren ; et al.	2006-06-15
Techniques for combining volatile and non-volatile programmable logic on an integrated circuit App 20060119384 - Camarota; Rafael ; et al.	2006-06-08
Techniques for implementing hardwired decoders in differential input circuits App 20060119386 - Ng; Bee Yee ; et al.	2006-06-08
Mask-programmable logic device with building block architecture Grant 6,988,258 - Tan , et al. January 17, 2	2006-01-17
Mask-programmable logic device with building block architecture App 20040111691 - Tan, Kim Pin ; et al.	2004-06-10
Programmable logic configuration device with configuration memory accessible to a second device Grant 6,605,960 - Veenstra , et al. August 12, 2	2003-08-12
Isolation testing scheme for multi-die packages Grant 6,599,764 - Ang , et al. July 29, 2	2003-07-29
Programmable Logic Configuration Device With Configuration Memory Accessible To A Second Device App 20030122577 - Veenstra, Kerry S. ; et al.	2003-07-03
Configuring a programmable logic device Grant 6,525,678 - Veenstra , et al. February 25, 2	2003-02-25