Anemikos; Theodoros E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Anemikos; Theodoros E..The latest application filed is for "on-going reliability monitoring of integrated circuit chips in the field".

Company Profile

0.10.9

Anemikos; Theodoros E. - Milton VT US
Anemikos; Theodoros E - Milton VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reliability test screen optimization Grant 9,429,619 - Anemikos , et al. August 30, 2	2016-08-30
On-going reliability monitoring of integrated circuit chips in the field Grant 9,310,426 - Anemikos , et al. April 12, 2	2016-04-12
On-going Reliability Monitoring Of Integrated Circuit Chips In The Field App 20140088947 - Anemikos; Theodoros E. ; et al.	2014-03-27
Reliability Test Screen Optimization App 20140039664 - ANEMIKOS; THEODOROS E. ; et al.	2014-02-06
Speed Binning For Dynamic And Adaptive Power Control App 20130113514 - Anemikos; Theodoros E. ; et al.	2013-05-09
Speed binning for dynamic and adaptive power control Grant 8,421,495 - Anemikos , et al. April 16, 2	2013-04-16
System and method for wireless and dynamic intra-process measurement of integrated circuit parameters Grant 8,239,811 - Anemikos , et al. August 7, 2	2012-08-07
System and method to optimize semiconductor power by integration of physical design timing and product performance measurements Grant 7,877,714 - Anemikos , et al. January 25, 2	2011-01-25
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point Grant 7,810,054 - Anemikos , et al. October 5, 2	2010-10-05
System And Method For Wireless And Dynamic Intra-process Measurement Of Integrated Circuit Parameters App 20090240452 - Anemikos; Theodoros E. ; et al.	2009-09-24
Method To Optimize Power By Tuning The Selective Voltage Binning Cut Point App 20090228843 - Anemikos; Theodoros E. ; et al.	2009-09-10
System And Method To Optimize Semiconductor Power By Integration Of Physical Design Timing And Product Performance Measurements App 20090217221 - ANEMIKOS; Theodoros E. ; et al.	2009-08-27
Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit App 20090115447 - Anemikos; Theodoros E. ; et al.	2009-05-07
Clock-skew tuning apparatus and method Grant 7,521,973 - Anemikos , et al. April 21, 2	2009-04-21
Design structure for monitoring cross chip delay variation on a semiconductor device Grant 7,487,487 - Polson , et al. February 3, 2	2009-02-03

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