| Patent | Date |
|---|
Method For Forming A Useful Substrate Trapping Structure
App 20220148908 - Augendre; Emmanuel ; et al. | 2022-05-12 |
Method For Manufacturing A Microelectronic Device
App 20220028728 - NIEBOJEWSKI; Heimanu ; et al. | 2022-01-27 |
3D circuit provided with mesa isolation for the ground plane zone
Grant 11,139,209 - Batude , et al. October 5, 2 | 2021-10-05 |
Device Comprising Wrap-gate Transistors And Method Of Manufacturing Such A Device
App 20210296398 - BARRAUD; Sylvain ; et al. | 2021-09-23 |
3d Memory And Manufacturing Process
App 20210193738 - BARRAUD; Sylvain ; et al. | 2021-06-24 |
Assembly for 3D circuit with superposed transistor levels
Grant 11,024,544 - Andrieu , et al. June 1, 2 | 2021-06-01 |
Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer
Grant 11,011,425 - Batude , et al. May 18, 2 | 2021-05-18 |
Image Sensor Formed In Sequential 3d Technology
App 20210082983 - Kadura; Lina ; et al. | 2021-03-18 |
Resistive 3d Memory
App 20210028231 - ANDRIEU; Francois | 2021-01-28 |
Integrated circuit chip with strained NMOS and PMOS transistors
Grant 10,777,680 - Berthelon , et al. Sept | 2020-09-15 |
3D SRAM circuit with double gate transistors with improved layout
Grant 10,741,565 - Andrieu , et al. A | 2020-08-11 |
3d Circuit Provided With Mesa Isolation For The Ground Plane Zone
App 20200203229 - BATUDE; Perrine ; et al. | 2020-06-25 |
Method Of Fabricating A Semiconductor Substrate Having A Stressed Semiconductor Region
App 20200194273 - REBOH; Shay ; et al. | 2020-06-18 |
3D circuit transistors with flipped gate
Grant 10,651,202 - Andrieu , et al. | 2020-05-12 |
Production Of A 3d Circuit With Upper Level Transistor Provided With A Gate Dielectric Derived From A Substrate Transfer
App 20200035561 - BATUDE; Perrine ; et al. | 2020-01-30 |
Optimized double-gate transistors and fabricating process
Grant 10,546,929 - Andrieu , et al. Ja | 2020-01-28 |
Integrated circuit comprising balanced cells at the active
Grant 10,504,897 - Andrieu , et al. Dec | 2019-12-10 |
Integrated Circuit Chip With Strained Nmos And Pmos Transistors
App 20190363190 - BERTHELON; Remy ; et al. | 2019-11-28 |
Integrated circuit including balanced cells limiting an active area
Grant 10,446,548 - Andrieu , et al. Oc | 2019-10-15 |
3d Sram Circuit With Double Gate Transistors With Improved Layout
App 20190312039 - Andrieu; Francois ; et al. | 2019-10-10 |
Integrated circuit chip with strained NMOS and PMOS transistors
Grant 10,418,486 - Berthelon , et al. Sept | 2019-09-17 |
Assembly For 3d Circuit With Superposed Transistor Levels
App 20190198397 - ANDRIEU; Francois ; et al. | 2019-06-27 |
3d Circuit Transistors With Flipped Gate
App 20190157300 - ANDRIEU; Francois ; et al. | 2019-05-23 |
Method of forming strained MOS transistors
Grant 10,263,110 - Berthelon , et al. | 2019-04-16 |
Transistors Double Grilles Optimises Et Procede De Fabrication
App 20190027560 - ANDRIEU; Francois ; et al. | 2019-01-24 |
Integrated Circuit Chip With Strained Nmos And Pmos Transistors
App 20180331221 - BERTHELON; Remy ; et al. | 2018-11-15 |
Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes
Grant 9,985,029 - Andrieu May 29, 2 | 2018-05-29 |
Integrated Circuit Including Balanced Cells Limiting An Active Area
App 20180083006 - ANDRIEU; Francois ; et al. | 2018-03-22 |
Integrated Circuit Including Balanced Cells Limiting An Active Area
App 20180083005 - ANDRIEU; Francois ; et al. | 2018-03-22 |
Integrated Circuit Comprising Transistors Having Different Threshold Voltages
App 20180026036 - ANDRIEU; Francois | 2018-01-25 |
Method of manufacturing a device with MOS transistors
Grant 9,876,032 - Chhun , et al. January 23, 2 | 2018-01-23 |
Method Of Forming Strained Mos Transistors
App 20170194498 - Berthelon; Remy ; et al. | 2017-07-06 |
Method Of Manufacturing A Device With Mos Transistors
App 20170117296 - Chhun; Sonarith ; et al. | 2017-04-27 |
Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors
Grant 9,558,957 - Andrieu , et al. January 31, 2 | 2017-01-31 |
Integrated circuit comprising PMOS transistors with different voltage thresholds
Grant 9,520,330 - Andrieu , et al. December 13, 2 | 2016-12-13 |
Process for fabricating SOI transistors for an increased integration density
Grant 9,514,996 - Andrieu , et al. December 6, 2 | 2016-12-06 |
Process For Fabricating Soi Transistors For An Increased Integration Density
App 20160307809 - ANDRIEU; Francois ; et al. | 2016-10-20 |
Integrated Circuit Comprising Pmos Transistors With Different Voltage Thresholds
App 20160197018 - ANDRIEU; Francois ; et al. | 2016-07-07 |
Method For Relaxing The Transverse Mechanical Stresses Within The Active Region Of A Mos Transistor, And Corresponding Integrated Circuit
App 20160099183 - Rideau; Denis ; et al. | 2016-04-07 |
Method for making a semiconductor structure with a buried ground plane
Grant 9,214,515 - Le Tiec , et al. December 15, 2 | 2015-12-15 |
Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers
Grant 9,147,750 - Morvan , et al. September 29, 2 | 2015-09-29 |
Method For Relaxing The Transverse Mechanical Stresses Within The Active Region Of A Mos Transistor, And Corresponding Integrated Circuit
App 20150097241 - Rideau; Denis ; et al. | 2015-04-09 |
Method for stressing a thin pattern and transistor fabrication method incorporating said method
Grant 8,853,023 - Morvan , et al. October 7, 2 | 2014-10-07 |
Method of adjusting the threshold voltage of a transistor by a buried trapping layer
Grant 8,809,964 - Andrieu , et al. August 19, 2 | 2014-08-19 |
Method For Making A Semiconductor Structure With A Buried Ground Plane
App 20130341649 - Le Tiec; Yannick ; et al. | 2013-12-26 |
Process For Fabricating A Transistor Comprising Nanoscale Semiconductor Features Using Block Copolymers
App 20130323888 - MORVAN; Simeon ; et al. | 2013-12-05 |
Method For Manufacturing A Substrate Provided With Different Active Areas And With Planar And Three-dimensional Transistors
App 20130309854 - ANDRIEU; Francois ; et al. | 2013-11-21 |
Method for making a semiconductor structure with a buried ground plane
Grant 8,501,588 - Le Tiec , et al. August 6, 2 | 2013-08-06 |
Method for Stressing a Thin Pattern and Transistor Fabrication Method Incorporating Said Method
App 20130196456 - MORVAN; Simeon ; et al. | 2013-08-01 |
Method For Making A Semiconductor Structure With A Buried Ground Plane
App 20110284870 - Le Tiec; Yannick ; et al. | 2011-11-24 |
Substrate Of The Semiconductor On Insulator Type With Intrinsic And Doped Diamond Layers
App 20110156057 - Mazellier; Jean-Paul ; et al. | 2011-06-30 |
Method Of Adjusting The Threshold Voltage Of A Transistor By A Buried Trapping Layer
App 20110001184 - Andrieu; Francois ; et al. | 2011-01-06 |
Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor
Grant 7,820,523 - Andrieu , et al. October 26, 2 | 2010-10-26 |
Fabrication of Active Areas of Different Natures Directly Onto an Insulator: Application to the Single or Double Gate Mos Transistor
App 20070246702 - Andrieu; Francois ; et al. | 2007-10-25 |
Combined microwave and optic rotary joint
Grant 5,140,289 - Andrieu , et al. August 18, 1 | 1992-08-18 |
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