Andresen; Bernhard H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Andresen; Bernhard H..The latest application filed is for "shared 5 volt tolerant esd protection circuit for low voltage cmos process".

Company Profile

0.18.1

Andresen; Bernhard H. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High voltage protection circuit for improved oxide reliability Grant 6,633,468 - Duvvury , et al. October 14, 2	2003-10-14
Voltage level shifter with testable cascode devices Grant 6,487,687 - Blake , et al. November 26, 2	2002-11-26
Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process App 20020027755 - Andresen, Bernhard H. ; et al.	2002-03-07
NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors Grant 6,310,379 - Andresen , et al. October 30, 2	2001-10-30
Method of designing fail-safe CMOS I/O buffers whose external nodes accept voltages higher than the maximum gate oxide operating voltage Grant 6,294,943 - Wall , et al. September 25, 2	2001-09-25
Testability circuit for cascode circuits used for high voltage interface Grant 6,211,693 - Andresen , et al. April 3, 2	2001-04-03
CMOS triggered NMOS ESD protection circuit Grant 6,147,538 - Andresen , et al. November 14, 2	2000-11-14
Free running digital phase lock loop Grant 6,115,439 - Andresen , et al. September 5, 2	2000-09-05
Lateral SCR structure for ESD protection in trench isolated technologies Grant 6,081,002 - Amerasekera , et al. June 27, 2	2000-06-27
Output buffer having quasi-failsafe operation Grant 6,040,708 - Blake , et al. March 21, 2	2000-03-21
Output buffer providing testability Grant 5,995,010 - Blake , et al. November 30, 1	1999-11-30
Fine resolution digital delay line with coarse and fine adjustment stages Grant 5,844,954 - Casasanta , et al. December 1, 1	1998-12-01
Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading Grant 5,621,335 - Andresen April 15, 1	1997-04-15
Fine resolution digital delay line with coarse and fine adjustment stages Grant 5,544,203 - Casasanta , et al. August 6, 1	1996-08-06
High performance digital phase locked loop Grant 5,355,037 - Andresen , et al. October 11, 1	1994-10-11
Non-loading output driver circuit Grant 5,004,936 - Andresen April 2, 1	1991-04-02
Test input demultiplexing circuit Grant 4,612,499 - Andresen , et al. September 16, 1	1986-09-16
Exposure information storage device for a photographic camera Grant 4,363,540 - Takishima , et al. December 14, 1	1982-12-14
Signal processing circuitry for a distance measuring system Grant 4,300,824 - Tokuda , et al. November 17, 1	1981-11-17

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