Andreev; Alexander E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Andreev; Alexander E..The latest application filed is for "system and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units".

Company Profile

0.118.57

Andreev; Alexander E. - San Jose CA
Andreev; Alexander E. - US
Andreev; Alexander E. - Moskovskata Oblast RU
Andreev; Alexander E. - Sunnyvale CA
Andreev; Alexander E. - Moskovskaga Oblast RU
ANDREEV, ALEXANDER E - MOSKOVSKAGA OBLAST RU
Andreev; Alexander E. - Moskovskaja Oblast RU
Andreev; Alexander E. - Proezd D.3 RU
Andreev; Alexander E. - Moskovskata RU
Andreev; Alexander E. - Moskovskaja RU

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units Grant 8,769,372 - Andreev , et al. July 1, 2	2014-07-01
System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors Grant 8,527,851 - Andreev , et al. September 3, 2	2013-09-03
Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same Grant 8,151,160 - Andreev , et al. April 3, 2	2012-04-03
System And Method For Assigning Code Blocks To Constituent Decoder Units In A Turbo Decoding System Having Parallel Decoding Units App 20120079345 - Andreev; Alexander E. ; et al.	2012-03-29
Memory mapping for parallel turbo decoding Grant 8,132,075 - Andreev , et al. March 6, 2	2012-03-06
System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units Grant 8,095,845 - Andreev , et al. January 10, 2	2012-01-10
Method and system for outputting a sequence of commands and data described by a flowchart Grant 8,006,209 - Nikitin , et al. August 23, 2	2011-08-23
Built in test controller with a downloadable testing program Grant 7,882,406 - Andreev , et al. February 1, 2	2011-02-01
Command language for memory testing Grant 7,856,577 - Andreev , et al. December 21, 2	2010-12-21
Digital Gaussian noise simulator Grant 7,822,099 - Nikitin , et al. October 26, 2	2010-10-26
System and method for using the universal multipole for the implementation of a configurable binary bose-chaudhuri-hocquenghem (BCH) encoder with variable number of errors App 20100031126 - Andreev; Alexander E. ; et al.	2010-02-04
Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data Grant 7,656,325 - Andreev February 2, 2	2010-02-02
Sequential tester for longest prefix search engines Grant 7,548,844 - Andreev , et al. June 16, 2	2009-06-16
Command Language For Memory Testing App 20090133003 - Andreev; Alexander E. ; et al.	2009-05-21
Method and system for outputting a sequence of commands and data described by a flowchart App 20090094571 - Nikitin; Andrey A. ; et al.	2009-04-09
RRAM memory error emulation Grant 7,493,519 - Andreev , et al. February 17, 2	2009-02-17
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,472,358 - Nikitin , et al. December 30, 2	2008-12-30
Memory BISR architecture for a slice Grant 7,430,694 - Andreev , et al. September 30, 2	2008-09-30
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,415,691 - Andreev , et al. August 19, 2	2008-08-19
Method and system for mapping netlist of integrated circuit to design Grant 7,404,166 - Andreev , et al. July 22, 2	2008-07-22
Method and system for converting netlist of integrated circuit between libraries Grant 7,380,223 - Panteleev , et al. May 27, 2	2008-05-27
Memory Mapping For Parallel Turbo Decoding App 20080049719 - Andreev; Alexander E. ; et al.	2008-02-28
Method for evaluating logic functions by logic circuits having optimized number of and/or switches Grant 7,328,423 - Nikitin , et al. February 5, 2	2008-02-05
Memory BISR controller architecture Grant 7,328,382 - Andreev , et al. February 5, 2	2008-02-05
Verification of RRAM tiling netlist Grant 7,315,993 - Nikitin , et al. January 1, 2	2008-01-01
Data stream frequency reduction and/or phase shift Grant 7,313,660 - Andreev , et al. December 25, 2	2007-12-25
Memory mapping for parallel turbo decoding Grant 7,305,593 - Andreev , et al. December 4, 2	2007-12-04
System and method for efficiently testing a large random access memory space Grant 7,305,597 - Andreev , et al. December 4, 2	2007-12-04
Sequential tester for longest prefix search engines App 20070276648 - Andreev; Alexander E. ; et al.	2007-11-29
RRAM communication system Grant 7,283,385 - Andreev , et al. October 16, 2	2007-10-16
Digital Gaussian Noise Simulator App 20070230621 - Nikitin; Andrey A. ; et al.	2007-10-04
Digital gaussian noise simulator Grant 7,263,470 - Nikitin , et al. August 28, 2	2007-08-28
Method for optimizing execution time of parallel processor programs Grant 7,257,807 - Nikitin , et al. August 14, 2	2007-08-14
Method and system for outputting a sequence of commands and data described by a flowchart App 20070169009 - Nikitin; Andrey A. ; et al.	2007-07-19
Search engine for large-width data Grant 7,231,383 - Andreev , et al. June 12, 2	2007-06-12
Process and apparatus for memory mapping Grant 7,219,321 - Nikitin , et al. May 15, 2	2007-05-15
Method and BIST architecture for fast memory testing in platform-based integrated circuit Grant 7,216,278 - Andreev , et al. May 8, 2	2007-05-08
Method and system for converting netlist of integrated circuit between libraries App 20070094621 - Panteleev; Pavel ; et al.	2007-04-26
RRAM memory error emulation App 20070094534 - Andreev; Alexander E. ; et al.	2007-04-26
Method and system for mapping netlist of integrated circuit to design App 20070094633 - Andreev; Alexander E. ; et al.	2007-04-26
Process and apparatus for placing cells in an IC floorplan Grant 7,210,113 - Andreev , et al. April 24, 2	2007-04-24
Sequential tester for longest prefix search engines Grant 7,200,785 - Andreev , et al. April 3, 2	2007-04-03
Compact custom layout for RRAM column controller Grant 7,194,717 - Andreev , et al. March 20, 2	2007-03-20
FIFO memory with single port memory modules for allowing simultaneous read and write operations Grant 7,181,563 - Andreev , et al. February 20, 2	2007-02-20
Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 Grant 7,167,886 - Gashkov , et al. January 23, 2	2007-01-23
Yield driven memory placement system Grant 7,168,052 - Andreev , et al. January 23, 2	2007-01-23
Decomposer for parallel turbo decoding, process and integrated circuit App 20060236194 - Andreev; Alexander E. ; et al.	2006-10-19
Process and apparatus for fast assignment of objects to a rectangle Grant 7,111,264 - Andreev , et al. September 19, 2	2006-09-19
Optimizing depths of circuits for Boolean functions Grant 7,103,868 - Nikitin , et al. September 5, 2	2006-09-05
Decomposer for parallel turbo decoding, process and integrated circuit Grant 7,096,413 - Andreev , et al. August 22, 2	2006-08-22
Built-in functional tester for search engines Grant 7,082,561 - Andreev , et al. July 25, 2	2006-07-25
Method and apparatus of IC implementation based on C++ language description Grant 7,082,593 - Nikitin , et al. July 25, 2	2006-07-25
Memory BISR controller architecture App 20060161804 - Andreev; Alexander E. ; et al.	2006-07-20
Memory BISR architecture for a slice App 20060161803 - Andreev; Alexander E. ; et al.	2006-07-20
Method and BIST architecture for fast memory testing in platform-based integrated circuit App 20060156088 - Andreev; Alexander E. ; et al.	2006-07-13
Integrated circuit and process for identifying minimum or maximum input value among plural inputs Grant 7,072,922 - Andreev , et al. July 4, 2	2006-07-04
RRAM communication system App 20060136775 - Andreev; Alexander E. ; et al.	2006-06-22
Controller architecture for memory mapping Grant 7,065,606 - Andreev , et al. June 20, 2	2006-06-20
Method for generating tech-library for logic function Grant 7,062,726 - Andreev , et al. June 13, 2	2006-06-13
Verification of RRAM tiling netlist App 20060117281 - Nikitin; Andrey A. ; et al.	2006-06-01
Pseudo-random one-to-one circuit synthesis Grant 7,050,582 - Andreev , et al. May 23, 2	2006-05-23
Decision function generator for a Viterbi decoder Grant 7,039,855 - Nikitin , et al. May 2, 2	2006-05-02
Process and apparatus for placement of cells in an IC during floorplan creation Grant 7,036,102 - Andreev , et al. April 25, 2	2006-04-25
FFS search and edit pipeline separation Grant 7,035,844 - Andreev , et al. April 25, 2	2006-04-25
Compact custom layout for RRAM column controller App 20060085777 - Andreev; Alexander E. ; et al.	2006-04-20
Table module compiler equivalent to ROM Grant 7,003,510 - Andreev , et al. February 21, 2	2006-02-21
Method and system for outputting a sequence of commands and data described by a flowchart App 20060020927 - Andreev; Alexander E. ; et al.	2006-01-26
Universal gates for ICs and transformation of netlists for their implementation Grant 6,988,252 - Andreev , et al. January 17, 2	2006-01-17
Yield driven memory placement system App 20060010092 - Andreev; Alexander E. ; et al.	2006-01-12
Process and apparatus for memory mapping App 20050240746 - Nikitin, Andrey A. ; et al.	2005-10-27
Process and apparatus for placing cells in an IC floorplan App 20050240889 - Andreev, Alexander E. ; et al.	2005-10-27
Built-in test for multiple memory circuits Grant 6,941,494 - Andreev , et al. September 6, 2	2005-09-06
User selectable editing protocol for fast flexible search engine Grant 6,941,314 - Andreev , et al. September 6, 2	2005-09-06
Clock tree synthesis with skew for memory devices Grant 6,941,533 - Andreev , et al. September 6, 2	2005-09-06
Optimization of adder based circuit architecture Grant 6,934,733 - Gashkov , et al. August 23, 2	2005-08-23
Method for evaluating logic functions by logic circuits having optimized number of and/or switches App 20050149302 - Nikitin, Andrey A. ; et al.	2005-07-07
Method for evaluating logic functions by logic circuits having optimized number of and/or switches Grant 6,901,573 - Nikitin , et al. May 31, 2	2005-05-31
FIFO memory with single port memory modules for allowing simultaneous read and write operations App 20050091465 - Andreev, Alexander E. ; et al.	2005-04-28
Process and apparatus for placement of cells in an IC during floorplan creation App 20050091625 - Andreev, Alexander E. ; et al.	2005-04-28
Memory that allows simultaneous read requests Grant 6,886,088 - Andreev , et al. April 26, 2	2005-04-26
Process and apparatus for fast assignment of objects to a rectangle App 20050086624 - Andreev, Alexander E. ; et al.	2005-04-21
Parallel processor language, method for translating C++ programs into this language, and method for optimizing execution time of parallel processor programs App 20050066321 - Nikitin, Andrey A. ; et al.	2005-03-24
Data stream frequency reduction and/or phase shift App 20050053182 - Andreev, Alexander E. ; et al.	2005-03-10
Controller architecture for memory mapping App 20050055527 - Andreev, Alexander E. ; et al.	2005-03-10
Memory mapping for parallel turbo decoding App 20050050426 - Andreev, Alexander E. ; et al.	2005-03-03
Universal gates for ICs and transformation of netlists for their implementation App 20050030067 - Andreev, Alexander E. ; et al.	2005-02-10
Netlist redundancy detection and global simplification Grant 6,848,094 - Andreev , et al. January 25, 2	2005-01-25
Method and apparatus of IC implementation based on C++ language description App 20050013155 - Nikitin, Andrey A. ; et al.	2005-01-20
Symbolic simulation driven netlist simplification Grant 6,842,750 - Andreev , et al. January 11, 2	2005-01-11
Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 App 20040225701 - Gashkov, Sergei B. ; et al.	2004-11-11
Digital gaussian noise simulator App 20040225481 - Nikitin, Andrey A. ; et al.	2004-11-11
Process for layout of memory matrices in integrated circuits Grant 6,804,811 - Andreev , et al. October 12, 2	2004-10-12
Method of decreasing instantaneous current without affecting timing Grant 6,795,954 - Andreev , et al. September 21, 2	2004-09-21
Sequential tester for longest prefix search engines App 20040181719 - Andreev, Alexander E. ; et al.	2004-09-16
Method for evaluating logic functions by logic circuits having optimized number of and/or switches App 20040177330 - Nikitin, Andrey A. ; et al.	2004-09-09
Prefix comparator Grant 6,785,699 - Andreev , et al. August 31, 2	2004-08-31
Decision function generator for a viterbi decoder App 20040153955 - Nikitin, Andrey A. ; et al.	2004-08-05
Process layout of buffer modules in integrated circuits Grant 6,760,896 - Andreev , et al. July 6, 2	2004-07-06
Netlist redundancy detection and global simplification App 20040128632 - Andreev, Alexander E. ; et al.	2004-07-01
Integrated circuit and process for identifying minimum or maximum input value among plural inputs App 20040117416 - Andreev, Alexander E. ; et al.	2004-06-17
Memory that allows simultaneous read requests App 20040107308 - Andreev, Egor A. ; et al.	2004-06-03
Decomposer for parallel turbo decoding, process and integrated circuit App 20040098653 - Andreev, Alexander E. ; et al.	2004-05-20
Optimizing depths of circuits for Boolean functions App 20040093578 - Nikitin, Andrey A. ; et al.	2004-05-13
Editing protocol for flexible search engines Grant 6,735,600 - Andreev , et al. May 11, 2	2004-05-11
Clock tree synthesis with skew for memory devices App 20040078766 - Andreev, Alexander E. ; et al.	2004-04-22
Method of decreasing instantaneous current without affecting timing App 20040076067 - Andreev, Alexander E. ; et al.	2004-04-22
Process For Layout Of Memory Matrices In Integrated Circuits App 20040060029 - Andreev, Alexander E. ; et al.	2004-03-25
Process layout of buffer modules in integrated circuits App 20040060027 - Andreev, Alexander E. ; et al.	2004-03-25
Process for fast cell placement in integrated circuit design Grant 6,704,915 - Andreev , et al. March 9, 2	2004-03-09
Optimization of comparator architecture Grant 6,691,283 - Gashkov , et al. February 10, 2	2004-02-10
Table module compiler equivalent to ROM App 20030236774 - Andreev, Alexander E. ; et al.	2003-12-25
Spanning tree method for K-dimensional space Grant 6,665,850 - Andreev , et al. December 16, 2	2003-12-16
Fast free memory address controller Grant 6,662,287 - Andreev , et al. December 9, 2	2003-12-09
Spanning Tree Method For K-dimensional Space App 20030221176 - Andreev, Alexander E. ; et al.	2003-11-27
User selectable editing protocol for fast flexible search engine App 20030208495 - Andreev, Alexander E. ; et al.	2003-11-06
Search engine for large-width data App 20030208475 - Andreev, Alexander E. ; et al.	2003-11-06
Built-in functional tester for search engines App 20030204799 - Andreev, Alexander E. ; et al.	2003-10-30
Symbolic simulation driven netlist simplification App 20030187815 - Andreev, Alexander E. ; et al.	2003-10-02
Optimal clock timing schedule for an integrated circuit Grant 6,615,397 - Andreev , et al. September 2, 2	2003-09-02
FFS search and edit pipline separation App 20030163442 - Andreev, Alexander E. ; et al.	2003-08-28
Fast flexible search engine for longest prefix match Grant 6,564,211 - Andreev , et al. May 13, 2	2003-05-13
Flexible search engine having sorted binary search tree for perfect match Grant 6,553,370 - Andreev , et al. April 22, 2	2003-04-22
Process, apparatus and program for transforming program language description of an IC to an RTL description Grant 6,487,698 - Andreev , et al. November 26, 2	2002-11-26
Process for fast cell placement in integrated circuit design App 20020124233 - Andreev, Alexander E. ; et al.	2002-09-05
Optimal clock timing schedule for an integrated circuit App 20020091983 - Andreev, Alexander E. ; et al.	2002-07-11
Hexagonal architecture Grant 6,407,434 - Rostoker , et al. June 18, 2	2002-06-18
Method and apparatus for parallel simultaneous global and detail routing Grant 6,324,674 - Andreev , et al. November 27, 2	2001-11-27
Advanced modular cell placement system Grant 6,292,929 - Scepanovic , et al. September 18, 2	2001-09-18
Method and apparatus for local optimization of the global routing Grant 6,289,495 - Raspopovic , et al. September 11, 2	2001-09-11
Method And Apparatus For Parallel Simultaneous Global And Detail Routing App 20010018759 - ANDREEV, ALEXANDER E. ; et al.	2001-08-30
Method and apparatus for coarse global routing Grant 6,260,183 - Raspopovic , et al. July 10, 2	2001-07-10
Net routing using basis element decomposition Grant 6,253,363 - Gasanov , et al. June 26, 2	2001-06-26
Advanced Modular Cell Placement System App 20010003843 - SCEPANOVIC, RANKO ; et al.	2001-06-14
Method and apparatus for parallel Steiner tree routing Grant 6,247,167 - Raspopovic , et al. June 12, 2	2001-06-12
Method and apparatus for minimization of process defects while routing Grant 6,230,306 - Raspopovic , et al. May 8, 2	2001-05-08
Advanced modular cell placement system with overlap remover with minimal noise Grant 6,223,332 - Scepanovic , et al. April 24, 2	2001-04-24
Method and apparatus for determining wire routing Grant 6,186,676 - Andreev , et al. February 13, 2	2001-02-13
Method and apparatus for hierarchical global routing descend Grant 6,175,950 - Scepanovic , et al. January 16, 2	2001-01-16
Memory-saving method and apparatus for partitioning high fanout nets Grant 6,154,874 - Scepanovic , et al. November 28, 2	2000-11-28
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints Grant 6,134,702 - Scepanovic , et al. October 17, 2	2000-10-17
Method and apparatus for horizontal congestion removal Grant 6,123,736 - Pavisic , et al. September 26, 2	2000-09-26
Triangular semiconductor or gate Grant 6,097,073 - Rostoker , et al. August 1, 2	2000-08-01
Advanced modular cell placement system with sinusoidal optimization Grant 6,085,032 - Scepanovic , et al. July 4, 2	2000-07-04
Method and apparatus for continuous column density optimization Grant 6,075,933 - Pavisic , et al. June 13, 2	2000-06-13
Method and apparatus for congestion driven placement Grant 6,070,108 - Andreev , et al. May 30, 2	2000-05-30
Method and apparatus for congestion removal Grant 6,068,662 - Scepanovic , et al. May 30, 2	2000-05-30
Advanced modular cell placement system Grant 6,067,409 - Scepanovic , et al. May 23, 2	2000-05-23
Method and apparatus for vertical congestion removal Grant 6,058,254 - Scepanovic , et al. May 2, 2	2000-05-02
Advanced modular cell placement system with overlap remover with minimal noise Grant 6,026,223 - Scepanovic , et al. February 15, 2	2000-02-15
Architecture having diamond shaped or parallelogram shaped cells Grant 5,973,376 - Rostoker , et al. October 26, 1	1999-10-26
Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles" Grant 5,909,376 - Scepanovic , et al. June 1, 1	1999-06-01
Advanced modular cell placement system with iterative one dimensional preplacement optimization Grant 5,892,688 - Scepanovic , et al. April 6, 1	1999-04-06
Tri-directional interconnect architecture for SRAM Grant 5,889,329 - Rostoker , et al. March 30, 1	1999-03-30
Hexagonal sense cell architecture Grant 5,872,380 - Rostoker , et al. February 16, 1	1999-02-16
Triangular semiconductor NAND gate Grant 5,864,165 - Rostoker , et al. January 26, 1	1999-01-26
Advanced modular cell placement system with universal affinity driven discrete placement optimization Grant 5,844,811 - Scepanovic , et al. December 1, 1	1998-12-01
Physical design automation system and method using monotonically improving linear clusterization Grant 5,838,585 - Scepanovic , et al. November 17, 1	1998-11-17
Triangular semiconductor "AND" gate device Grant 5,834,821 - Rostoker , et al. November 10, 1	1998-11-10
Advanced modular cell placement system with wire length driven affinity system Grant 5,831,863 - Scepanovic , et al. November 3, 1	1998-11-03
CAD for hexagonal architecture Grant 5,822,214 - Rostoker , et al. October 13, 1	1998-10-13
Transistors having dynamically adjustable characteristics Grant 5,811,863 - Rostoker , et al. September 22, 1	1998-09-22
Polydirectional non-orthoginal three layer interconnect architecture Grant 5,808,330 - Rostoker , et al. September 15, 1	1998-09-15
Advanced modular cell placement system with cell placement crystallization Grant 5,808,899 - Scepanovic , et al. September 15, 1	1998-09-15
Hexagonal SRAM architecture Grant 5,801,422 - Rostoker , et al. September 1, 1	1998-09-01
Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization Grant 5,796,625 - Scepanovic , et al. August 18, 1	1998-08-18
Hexagonal architecture with triangular shaped cells Grant 5,789,770 - Rostoker , et al. August 4, 1	1998-08-04
Hexagonal field programmable gate array architecture Grant 5,777,360 - Rostoker , et al. July 7, 1	1998-07-07
Hexagonal DRAM array Grant 5,742,086 - Rostoker , et al. April 21, 1	1998-04-21
Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization Grant 5,712,793 - Scepanovic , et al. January 27, 1	1998-01-27
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints Grant 5,699,265 - Scepanovic , et al. December 16, 1	1997-12-16
Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters Grant 5,661,663 - Scepanovic , et al. August 26, 1	1997-08-26
Microelectronic integrated circuit including triangular CMOS "nand" gate device Grant 5,650,653 - Rostoker , et al. July 22, 1	1997-07-22
Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry Grant 5,578,840 - Scepanovic , et al. November 26, 1	1996-11-26