An; Judy Xilin

Patent Applications and Registrations

Patent applications and USPTO patent grants for An; Judy Xilin.The latest application filed is for "double and triple gate mosfet devices and methods for making same".

Company Profile

0.44.12

An; Judy Xilin - San Jose CA
An; Judy Xilin - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Double and triple gate MOSFET devices and methods for making same Grant 8,580,660 - Lin , et al. November 12, 2	2013-11-12
Germanium MOSFET devices and methods for making same Grant 8,334,181 - An , et al. December 18, 2	2012-12-18
Double And Triple Gate Mosfet Devices And Methods For Making Same App 20120252193 - LIN; Ming-Ren ; et al.	2012-10-04
Double and triple gate MOSFET devices and methods for making same Grant 8,222,680 - Lin , et al. July 17, 2	2012-07-17
Germanium MOSFET devices and methods for making same Grant 7,781,810 - An , et al. August 24, 2	2010-08-24
FinFET device with multiple fin structures Grant 7,679,134 - Buynoski , et al. March 16, 2	2010-03-16
Integrated circuit tester information processing system for nonlinear mobility model for strained device Grant 7,630,850 - Topaloglu , et al. December 8, 2	2009-12-08
Integrated circuit tester information processing system Grant 7,610,160 - Suryagandh , et al. October 27, 2	2009-10-27
Integrated Circuit Tester Information Processing System For Nonlinear Mobility Model For Strained Device App 20090099829 - Topaloglu; Rasit Onur ; et al.	2009-04-16
Integrated Circuit Tester Information Processing System App 20090076750 - Suryagandh; Sushant S. ; et al.	2009-03-19
FinFET device with multiple channels Grant 7,432,557 - Buynoski , et al. October 7, 2	2008-10-07
Formation of semiconductor devices to achieve <100> channel orientation Grant 7,432,558 - Ahmed , et al. October 7, 2	2008-10-07
Tri-gate and gate around MOSFET devices and methods for making same Grant 7,259,425 - An , et al. August 21, 2	2007-08-21
Method of manufacturing a semiconductor device having a fin structure Grant 7,179,692 - Yu , et al. February 20, 2	2007-02-20
Germanium MOSFET devices and methods for making same Grant 7,148,526 - An , et al. December 12, 2	2006-12-12
Semiconductor device having a gate structure surrounding a fin Grant 6,960,804 - Yang , et al. November 1, 2	2005-11-01
Narrow fin FinFET Grant 6,921,963 - Krivokapic , et al. July 26, 2	2005-07-26
Semiconductor device having a thin fin and raised source/drain areas Grant 6,911,697 - Wang , et al. June 28, 2	2005-06-28
Strained channel FinFET Grant 6,897,527 - Dakshina-Murthy , et al. May 24, 2	2005-05-24
Method for forming multiple fins in a semiconductor device Grant 6,872,647 - Yu , et al. March 29, 2	2005-03-29
Method for forming tri-gate FinFET with mesa isolation Grant 6,855,583 - Krivokapic , et al. February 15, 2	2005-02-15
Double-gate semiconductor device Grant 6,853,020 - Yu , et al. February 8, 2	2005-02-08
Method of manufacturing a semiconductor device having a U-shaped gate structure App 20050006666 - Yu, Bin ; et al.	2005-01-13
Two transistor NOR device Grant 6,842,048 - Krivokapic , et al. January 11, 2	2005-01-11
Semiconductor device having a U-shaped gate structure Grant 6,833,588 - Yu , et al. December 21, 2	2004-12-21
Method for forming a gate in a FinFET device Grant 6,815,268 - Yu , et al. November 9, 2	2004-11-09
Strained channel finfet Grant 6,803,631 - Dakshina-Murthy , et al. October 12, 2	2004-10-12
Strained channel FinFET App 20040195627 - Dakshina-Murthy, Srikanteswara ; et al.	2004-10-07
Narrow fin finfet App 20040197975 - Krivokapic, Zoran ; et al.	2004-10-07
Asymmetrical double gate or all-around gate MOSFET devices and methods for making same Grant 6,800,885 - An , et al. October 5, 2	2004-10-05
Tri-gate and gate around MOSFET devices and methods for making same App 20040145000 - An, Judy Xilin ; et al.	2004-07-29
Strained Channel Finfet App 20040145019 - Dakshina-Murthy, Srikanteswara ; et al.	2004-07-29
Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding Grant 6,765,227 - Yu , et al. July 20, 2	2004-07-20
FinFET-based SRAM cell Grant 6,765,303 - Krivokapic , et al. July 20, 2	2004-07-20
Narrow fin FinFET Grant 6,762,483 - Krivokapic , et al. July 13, 2	2004-07-13
Two transistor nor device App 20040100306 - Krivokapic, Zoran ; et al.	2004-05-27
Semiconductor device having a U-shaped gate structure App 20040075121 - Yu, Bin ; et al.	2004-04-22
Double and triple gate MOSFET devices and methods for making same App 20040075122 - Lin, Ming-Ren ; et al.	2004-04-22
Method for forming channels in a finfet device Grant 6,716,686 - Buynoski , et al. April 6, 2	2004-04-06
Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure Grant 6,717,212 - Ju , et al. April 6, 2	2004-04-06
Uniformly doped source/drain junction in a double-gate MOSFET Grant 6,716,690 - Wang , et al. April 6, 2	2004-04-06
Double spacer FinFET formation Grant 6,709,982 - Buynoski , et al. March 23, 2	2004-03-23
Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation. Grant 6,706,614 - An , et al. March 16, 2	2004-03-16
Method for forming multiple structures in a semiconductor device Grant 6,706,571 - Yu , et al. March 16, 2	2004-03-16
Self-aligned floating body control for SOI device through leakage enhanced buried oxide Grant 6,509,613 - En , et al. January 21, 2	2003-01-21
Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure App 20020185685 - Ju, Dong-Hyuk ; et al.	2002-12-12
Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness Grant 6,448,114 - An , et al. September 10, 2	2002-09-10
Method and apparatus for making MOSFETs with elevated source/drain extensions Grant 6,445,042 - Yu , et al. September 3, 2	2002-09-03
Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation Grant 6,445,016 - An , et al. September 3, 2	2002-09-03
Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness Grant 6,414,355 - An , et al. July 2, 2	2002-07-02
MOS transistor with minimal overlap between gate and source/drain extensions Grant 6,265,256 - An , et al. July 24, 2	2001-07-24
MOS transistor with stepped gate insulator Grant 6,225,661 - An , et al. May 1, 2	2001-05-01
Method and apparatus for making mosfet's with elevated source/drain extensions Grant 6,187,642 - Yu , et al. February 13, 2	2001-02-13
MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions Grant 6,107,667 - An , et al. August 22, 2	2000-08-22
Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET Grant 5,985,726 - Yu , et al. November 16, 1	1999-11-16