AMUNDSON; Michael D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for AMUNDSON; Michael D..The latest application filed is for "method to adjust alley gap between large blocks for floorplan optimization".

Company Profile

0.12.15

AMUNDSON; Michael D. - Oronoco MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method To Adjust Alley Gap Between Large Blocks For Floorplan Optimization App 20170169155 - AMUNDSON; Michael D. ; et al.	2017-06-15
Analysis Of Project Management App 20160210577 - Amundson; Michael D. ; et al.	2016-07-21
Analysis Of Project Management App 20160210571 - Amundson; Michael D. ; et al.	2016-07-21
Analysis Of Project Management App 20160210573 - Amundson; Michael D. ; et al.	2016-07-21
Implementing enhanced physical design quality using historical placement analytics Grant 9,223,923 - Amundson , et al. December 29, 2	2015-12-29
Implementing enhanced physical design quality using historical placement analytics Grant 9,218,445 - Amundson , et al. December 22, 2	2015-12-22
Implementing Enhanced Physical Design Quality Using Historical Placement Analytics App 20150205899 - Amundson; Michael D. ; et al.	2015-07-23
Implementing Enhanced Physical Design Quality Using Historical Placement Analytics App 20150205900 - Amundson; Michael D. ; et al.	2015-07-23
Specifying circuit level connectivity during circuit design synthesis Grant 8,839,162 - Amundson , et al. September 16, 2	2014-09-16
Clock alias for timing analysis of an integrated circuit design Grant 8,683,402 - Amundson , et al. March 25, 2	2014-03-25
Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition Grant 8,448,113 - Amundson , et al. May 21, 2	2013-05-21
Clock alias for timing analysis of an integrated circuit design Grant 8,438,514 - Amundson , et al. May 7, 2	2013-05-07
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20130074021 - Amundson; Michael D. ; et al.	2013-03-21
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20130074022 - Amundson; Michael D. ; et al.	2013-03-21
Clock alias for timing analysis of an integrated circuit design Grant 8,250,515 - Amundson , et al. August 21, 2	2012-08-21
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20120204138 - Amundson; Michael D. ; et al.	2012-08-09
Specifying Circuit Level Connectivity During Circuit Design Synthesis App 20120017186 - Amundson; Michael D. ; et al.	2012-01-19
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20110271245 - Amundson; Michael D. ; et al.	2011-11-03
Efficiently Applying A Single Timing Assertion To Multiple Timing Points In A Circuit App 20110265052 - AMUNDSON; MICHAEL D. ; et al.	2011-10-27
Control of design automation process Grant 8,001,496 - Amundson August 16, 2	2011-08-16
Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization Grant 7,895,544 - Amundson February 22, 2	2011-02-22
Method To Graphically Identify Registers With Unbalanced Slack As Part Of Placement Driven Synthesis Optimization App 20100064264 - Amundson; Michael D.	2010-03-11
Method and System for Generating an Accurate Physical Realization for an Integrated Circuit Having Incomplete Physical Constraints App 20090241082 - Amundson; Michael D. ; et al.	2009-09-24
Control of Design Automation Process App 20090217184 - Amundson; Michael D.	2009-08-27

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