Aminpur; Massud

Patent Applications and Registrations

Patent applications and USPTO patent grants for Aminpur; Massud.The latest application filed is for "technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics".

Company Profile

0.15.13

Aminpur; Massud - Hopewell Junction NY
Aminpur; Massud - Crolles FR
Aminpur; Massud - Dresden DE
Aminpur; Massud - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches Grant 8,101,524 - Frohberg , et al. January 24, 2	2012-01-24
Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics Grant 7,763,547 - Werner , et al. July 27, 2	2010-07-27
Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress Grant 7,517,816 - Frohberg , et al. April 14, 2	2009-04-14
Technique for controlling mechanical stress in a channel region by spacer removal Grant 7,314,793 - Frohberg , et al. January 1, 2	2008-01-01
Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics Grant 7,309,654 - Schaller , et al. December 18, 2	2007-12-18
System for forming a semiconductor device and method thereof Grant 7,256,113 - Hellig , et al. August 14, 2	2007-08-14
Technique For Reducing Etch Damage During The Formation Of Vias And Trenches In Interlayer Dielectrics App 20070004214 - Schaller; Matthias ; et al.	2007-01-04
Technique for forming a gate electrode by using a hard mask Grant 7,151,055 - Aminpur , et al. December 19, 2	2006-12-19
Method of forming a gate electrode on a semiconductor device and a device incorporating same Grant 7,087,509 - Roche , et al. August 8, 2	2006-08-08
Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics App 20060172525 - Werner; Thomas ; et al.	2006-08-03
Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches App 20060046495 - Frohberg; Kai ; et al.	2006-03-02
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer Grant 7,005,380 - Aminpur , et al. February 28, 2	2006-02-28
Techique for controlling mechanical stress in a channel region by spacer removal App 20050266639 - Frohberg, Kai ; et al.	2005-12-01
Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress App 20050263825 - Frohberg, Kai ; et al.	2005-12-01
Technique for forming a gate electrode by using a hard mask App 20050118801 - Aminpur, Massud ; et al.	2005-06-02
Barrier layer for a copper metallization layer including a low-k dielectric Grant 6,893,956 - Ruelke , et al. May 17, 2	2005-05-17
SOI field effect transistor element having an ohmic substrate contact App 20040217421 - Aminpur, Massud ; et al.	2004-11-04
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer App 20040121599 - Aminpur, Massud ; et al.	2004-06-24
Barrier layer for a copper metallization layer including a low k dielectric App 20040084680 - Ruelke, Hartmut ; et al.	2004-05-06
Channel isolation using dielectric isolation structures Grant 6,727,558 - Duane , et al. April 27, 2	2004-04-27
Method for endpoint detection during etch App 20040043618 - Hellig, Kay ; et al.	2004-03-04
Photosensitive bottom anti-reflective coating Grant 6,699,641 - Hellig , et al. March 2, 2	2004-03-02
Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits App 20040023499 - Hellig, Kay ; et al.	2004-02-05
Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side App 20030232466 - Zistl, Christian ; et al.	2003-12-18
SOI transistor element having an improved backside contact and method of forming the same App 20030203546 - Burbach, Gert ; et al.	2003-10-30
Method of forming a hard mask for halo implants Grant 6,624,035 - Luning , et al. September 23, 2	2003-09-23
Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors Grant 6,617,219 - Duane , et al. September 9, 2	2003-09-09
Control trimming of hard mask for sub-100 nanometer transistor gate Grant 6,482,726 - Aminpur , et al. November 19, 2	2002-11-19

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