| Patent | Date |
|---|
Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
Grant 5,966,728 - Amini , et al. October 12, 1 | 1999-10-12 |
Computer system with varied data transfer speeds between system components and memory
Grant 5,761,533 - Aldereguia , et al. June 2, 1 | 1998-06-02 |
Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device
Grant 5,673,414 - Amini , et al. September 30, 1 | 1997-09-30 |
Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required
Grant 5,659,696 - Amini , et al. August 19, 1 | 1997-08-19 |
Bidirectional data buffer for a bus-to-bus interface unit in a computer system
Grant 5,644,729 - Amini , et al. July 1, 1 | 1997-07-01 |
Power management of DMA slaves with DMA traps
Grant 5,619,729 - Bland , et al. April 8, 1 | 1997-04-08 |
Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus)
Grant 5,581,714 - Amini , et al. December 3, 1 | 1996-12-03 |
Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system
Grant 5,564,026 - Amini , et al. October 8, 1 | 1996-10-08 |
Expandable high performance FIFO design which includes memory cells having respective cell multiplexors
Grant 5,551,009 - Amini , et al. August 27, 1 | 1996-08-27 |
Dynamic bus sizing of DMA transfers
Grant 5,548,786 - Amini , et al. August 20, 1 | 1996-08-20 |
System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus
Grant 5,544,346 - Amini , et al. August 6, 1 | 1996-08-06 |
System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
Grant 5,542,055 - Amini , et al. July 30, 1 | 1996-07-30 |
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
Grant 5,522,050 - Amini , et al. May 28, 1 | 1996-05-28 |
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
Grant 5,499,346 - Amini , et al. March 12, 1 | 1996-03-12 |
System direct memory access (DMA) support logic for PCI based computer system
Grant 5,450,551 - Amini , et al. September 12, 1 | 1995-09-12 |
Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
Grant 5,448,703 - Amini , et al. September 5, 1 | 1995-09-05 |
Arbitration logic for multiple bus computer system
Grant 5,396,602 - Amini , et al. March 7, 1 | 1995-03-07 |
DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
Grant 5,381,538 - Amini , et al. January 10, 1 | 1995-01-10 |
Error detection and recovery in a DMA controller
Grant 5,333,274 - Amini , et al. July 26, 1 | 1994-07-26 |
Parity error detection and recovery
Grant 5,313,627 - Amini , et al. May 17, 1 | 1994-05-17 |
Controlling bus allocation using arbitration hold
Grant 5,301,282 - Amini , et al. April 5, 1 | 1994-04-05 |
Arbitration control logic for computer system having dual bus architecture
Grant 5,265,211 - Amini , et al. November 23, 1 | 1993-11-23 |
Bus interface logic for computer system having dual bus architecture
Grant 5,255,374 - Aldereguia , et al. October 19, 1 | 1993-10-19 |
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