Amedeo; Robert J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Amedeo; Robert J..The latest application filed is for "circuit having logic state retention during power-down and method therefor".
- Amedeo; Robert J. - Austin TX
| Patent | Date |
|---|---|
| Circuit having logic state retention during power-down and method therefor Grant 7,619,440 - Amedeo , et al. November 17, 2 | 2009-11-17 |
| Circuit Having Logic State Retention During Power-down And Method Therefor App 20090189636 - Amedeo; Robert J. ; et al. | 2009-07-30 |
| Digital timer apparatus and method Grant 5,325,341 - Viot , et al. June 28, 1 | 1994-06-28 |
| Data processing system which generates a waveform with improved pulse width resolution Grant 5,293,628 - Langan , et al. March 8, 1 | 1994-03-08 |
| High speed output buffer circuit with overlap current control Grant 5,089,722 - Amedeo February 18, 1 | 1992-02-18 |
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