loadpatents
name:-0.012256860733032
name:-0.0089600086212158
name:-0.0018019676208496
AMARNATH; Kuldeep Patent Filings

AMARNATH; Kuldeep

Patent Applications and Registrations

Patent applications and USPTO patent grants for AMARNATH; Kuldeep.The latest application filed is for "systems and methods for constructing programmable credential and security cards".

Company Profile
2.11.13
  • AMARNATH; Kuldeep - Fremont CA
  • Amarnath; Kuldeep - Santa Clara CA
  • Amarnath; Kuldeep - San Jose CA
  • Amarnath; Kuldeep - Beacon NY US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Systems And Methods For Constructing Programmable Credential And Security Cards
App 20190258911 - AMARNATH; Kuldeep ;   et al.
2019-08-22
Systems and methods for creating dynamic programmable magnetic stripes
Grant 10,127,488 - Amarnath , et al. November 13, 2
2018-11-13
Systems And Methods For Constructing Programmable Credential and Security Cards
App 20160224879 - Amarnath; Kuldeep ;   et al.
2016-08-04
Systems And Methods For Creating Dynamic Programmable Credential and Security Cards
App 20160189127 - Amarnath; Kuldeep ;   et al.
2016-06-30
Systems And Methods For Creating Dynamic Programmable Magnetic Stripes
App 20160188916 - Amarnath; Kuldeep ;   et al.
2016-06-30
Semiconductor Devices With A Replacement Gate Structure Having A Recessed Channel
App 20150270346 - Amarnath; Kuldeep ;   et al.
2015-09-24
Methods of forming replacement gate structures with a recessed channel
Grant 9,099,492 - Amarnath , et al. August 4, 2
2015-08-04
Methods for fabricating integrated circuits with drift regions and replacement gates
Grant 8,940,608 - Feng , et al. January 27, 2
2015-01-27
Methods For Fabricating Integrated Circuits With Drift Regions And Replacement Gates
App 20130344669 - Feng; Jia ;   et al.
2013-12-26
Double-sided semiconductor structure using through-silicon vias
Grant 8,610,281 - Nguyen , et al. December 17, 2
2013-12-17
Self-aligned embedded SiGe structure and method of manufacturing the same
Grant 8,598,009 - Greene , et al. December 3, 2
2013-12-03
Methods Of Forming Replacement Gate Structures With A Recessed Channel
App 20130248985 - Amarnath; Kuldeep ;   et al.
2013-09-26
Methods of forming FinFET semiconductor devices with different fin heights
Grant 8,361,894 - Hargrove , et al. January 29, 2
2013-01-29
SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME
App 20120208337 - Greene; Brian J. ;   et al.
2012-08-16
Self-aligned embedded SiGe structure and method of manufacturing the same
Grant 8,222,673 - Greene , et al. July 17, 2
2012-07-17
SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME
App 20110298008 - Greene; Brian J. ;   et al.
2011-12-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed