Alter; Martin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Alter; Martin.The latest application filed is for "ldmos transistor with asymmetric spacer as gate".

Company Profile

0.18.23

Alter; Martin - Los Altos CA
Alter; Martin - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
LDMOS transistor with asymmetric spacer as gate Grant 8,889,518 - Alter , et al. November 18, 2	2014-11-18
Ldmos Transistor With Asymmetric Spacer As Gate App 20130316508 - Alter; Martin ; et al.	2013-11-28
LDMOS transistor with asymmetric spacer as gate Grant 8,525,257 - Alter , et al. September 3, 2	2013-09-03
System for vertical DMOS with slots Grant 8,227,860 - Alter , et al. July 24, 2	2012-07-24
Diode having high breakdown voltage and low on-resistance Grant 7,960,754 - Alter June 14, 2	2011-06-14
LDMOS transistor with asymmetric spacer as gate App 20110115017 - Alter; Martin ; et al.	2011-05-19
Seal ring for mixed circuitry semiconductor devices Grant 7,843,019 - Mallikarjunaswamy , et al. November 30, 2	2010-11-30
Diode Having High Breakdown Voltage and Low on-Resistance App 20100230774 - Alter; Martin	2010-09-16
System For Vertical Dmos With Slots App 20100065906 - ALTER; Martin ; et al.	2010-03-18
MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness App 20100032753 - Alter; Martin	2010-02-11
NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness App 20090283843 - Alter; Martin	2009-11-19
Power FET with low on-resistance using merged metal layers Grant 7,586,132 - Alter , et al. September 8, 2	2009-09-08
Transistors fabricated using a reduced cost CMOS process Grant 7,573,098 - Alter August 11, 2	2009-08-11
LDO regulator with ground connection through package bottom Grant 7,501,693 - Chu , et al. March 10, 2	2009-03-10
N-channel MOS Transistor Fabricated Using A Reduced Cost CMOS Process App 20090032850 - Alter; Martin	2009-02-05
Seal ring for mixed circuitry semiconductor devices Grant 7,485,549 - Mallikarjunaswamy , et al. February 3, 2	2009-02-03
Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics App 20090026578 - Wu; Schyi-yi ; et al.	2009-01-29
Power FET With Low On-Resistance Using Merged Metal Layers App 20080303097 - Alter; Martin ; et al.	2008-12-11
High Voltage Metal-On-Passivation Capacitor App 20080185682 - Alter; Martin	2008-08-07
LDO Regulator with Ground Connection Through Package Bottom App 20080135994 - Chu; George ; et al.	2008-06-12
Power FET with embedded body pickup Grant 7,315,052 - Alter January 1, 2	2008-01-01
Transistor process using a double-epitaxial layer for reduced capacitance App 20070246790 - Zinn; Raymond ; et al.	2007-10-25
Power FET with embedded body pickup App 20070205461 - Alter; Martin	2007-09-06
Schottky Diode Device with Aluminum Pickup of Backside Cathode App 20070138648 - Vinn; Chuck ; et al.	2007-06-21
Integrating chip scale packaging metallization into integrated circuit die structures Grant 7,211,893 - Alter , et al. May 1, 2	2007-05-01
Schottky diode device with aluminum pickup of backside cathode Grant 7,195,952 - Vinn , et al. March 27, 2	2007-03-27
Seal ring for mixed circuitry semiconductor devices App 20070001240 - Mallikarjunaswamy; Shekar ; et al.	2007-01-04
Seal ring for mixed circuitry semiconductor devices App 20070001004 - Mallikarjunaswamy; Shekar ; et al.	2007-01-04
Seal ring for mixed circuitry semiconductor devices Grant 7,145,211 - Mallikarjunaswamy , et al. December 5, 2	2006-12-05
Schottky diode device with aluminium pickup of backside cathode App 20060216855 - Vinn; Chuck ; et al.	2006-09-28
Seal ring for mixed circuitry semiconductor devices App 20060012003 - Mallikarjunaswamy; Shekar ; et al.	2006-01-19
Integrating chip scale packaging metallization into integrated circuit die structures Grant 6,917,105 - Alter July 12, 2	2005-07-12
Semiconductor devices integrated with wafer-level packaging App 20050127505 - Alter, Martin	2005-06-16
Integrating chip scale packaging metallization into integrated circuit die structures Grant 6,900,538 - Alter , et al. May 31, 2	2005-05-31
Integrating chip scale packaging metallization into integrated circuit die structures App 20050062156 - Alter, Martin ; et al.	2005-03-24
Semiconductor devices integrated with wafer-level packaging App 20050046022 - Alter, Martin	2005-03-03
Integrating chip scale packaging metallization into integrated circuit die structures App 20040245631 - Alter, Martin	2004-12-09
Integrating chip scale packaging metallization into integrated circuit die structures App 20040245633 - Alter, Martin ; et al.	2004-12-09
Programmable optical array Grant 6,711,046 - Alter March 23, 2	2004-03-23
Zener-like trim device in polysilicon Grant 6,621,138 - Alter September 16, 2	2003-09-16

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