Alpert; Charles J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Alpert; Charles J..The latest application filed is for "fault-tolerant power-driven synthesis".

Company Profile

5.60.55

Alpert; Charles J. - Austin TX
Alpert; Charles J - Austin TX
Alpert; Charles J. - Cedar Park TX
Alpert; Charles J - Cedar Park TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fault-tolerant power-driven synthesis Grant 11,301,757 - Alpert , et al. April 12, 2	2022-04-12
Power driven synaptic network synthesis Grant 10,679,120 - Alpert , et al.	2020-06-09
Fault-tolerant Power-driven Synthesis App 20200097833 - Alpert; Charles J. ; et al.	2020-03-26
Fault-tolerant power-driven synthesis Grant 10,552,740 - Alpert , et al. Fe	2020-02-04
Power-driven synthesis under latency constraints Grant 10,354,183 - Alpert , et al. July 16, 2	2019-07-16
Efficient C.sub.eff model for gate output slew computation in early synthesis Grant 9,946,824 - Alpert , et al. April 17, 2	2018-04-17
Addressing coupled noise-based violations with buffering in a batch environment Grant 9,875,326 - Alpert , et al. January 23, 2	2018-01-23
Addressing Coupled Noise-Based Violations with Buffering in a Batch Environment App 20170161407 - Alpert; Charles J. ; et al.	2017-06-08
Element placement in circuit design based on preferred location Grant 9,524,363 - Alpert , et al. December 20, 2	2016-12-20
Fault-tolerant Power-driven Synthesis App 20160132769 - Alpert; Charles J. ; et al.	2016-05-12
Power-driven Synthesis Under Latency Constraints App 20160132765 - Alpert; Charles J. ; et al.	2016-05-12
Power Driven Synaptic Network Synthesis App 20160132767 - Alpert; Charles J. ; et al.	2016-05-12
Boundary latch and logic placement to satisfy timing constraints Grant 9,098,669 - Alpert , et al. August 4, 2	2015-08-04
Automatic generation of wire tag lists for a metal stack Grant 9,092,591 - Alpert , et al. July 28, 2	2015-07-28
Boundary Latch And Logic Placement To Satisfy Timing Constraints App 20150199465 - Alpert; Charles J. ; et al.	2015-07-16
Computer-based modeling of integrated circuit congestion and wire distribution for products and services Grant 9,047,436 - Alpert , et al. June 2, 2	2015-06-02
Efficient Ceff Model For Gate Output Slew Computation In Early Synthesis App 20150143326 - Alpert; Charles J. ; et al.	2015-05-21
Computer-based Modeling Of Integrated Circuit Congestion And Wire Distribution For Products And Services App 20150113491 - Alpert; Charles J. ; et al.	2015-04-23
Structured placement of latches/flip-flops to minimize clock power in high-performance designs Grant 8,954,912 - Alpert , et al. February 10, 2	2015-02-10
Computer-based modeling of integrated circuit congestion and wire distribution for products and services Grant 8,949,762 - Alpert , et al. February 3, 2	2015-02-03
Routing centric design closure Grant 8,826,215 - Alpert , et al. September 2, 2	2014-09-02
Automatic Generation of Wire Tag Lists for a Metal Stack App 20140223397 - Alpert; Charles J. ; et al.	2014-08-07
Placement of structured nets Grant 8,793,636 - Alpert , et al. July 29, 2	2014-07-29
Post-placement cell shifting Grant 8,782,584 - Alpert , et al. July 15, 2	2014-07-15
Automatic Generation of Wire Tag Lists for a Metal Stack App 20140195998 - Alpert; Charles J. ; et al.	2014-07-10
Automatic generation of wire tag lists for a metal stack Grant 8,769,468 - Alpert , et al. July 1, 2	2014-07-01
Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design Grant 8,769,457 - Alpert , et al. July 1, 2	2014-07-01
Structured Placement Of Latches/flip-flops To Minimize Clock Power In High-performance Designs App 20140149957 - Alpert; Charles J. ; et al.	2014-05-29
Electronic design automation object placement with partially region-constrained objects Grant 8,683,411 - Alpert , et al. March 25, 2	2014-03-25
Clock optimization with local clock buffer control optimization Grant 8,667,441 - Alpert , et al. March 4, 2	2014-03-04
Separate Refinement Of Local Wirelength And Local Module Density In Intermediate Placement Of An Integrated Circuit Design App 20140007036 - Alpert; Charles J. ; et al.	2014-01-02
Post-placement Cell Shifting App 20130346938 - Alpert; Charles J ; et al.	2013-12-26
Element Placement In Circuit Design Based On Preferred Location App 20130326455 - Alpert; Charles J. ; et al.	2013-12-05
Local objective optimization in global placement of an integrated circuit design Grant 8,595,675 - Alpert , et al. November 26, 2	2013-11-26
Datapath placement using tiered assignment Grant 8,589,848 - Alpert , et al. November 19, 2	2013-11-19
Evaluating routing congestion based on average global edge congestion histograms Grant 8,584,070 - Alpert , et al. November 12, 2	2013-11-12
Datapath Placement Using Tiered Assignment App 20130283225 - Alpert; Charles J. ; et al.	2013-10-24
Routability using multiplexer structures Grant 8,539,400 - Alpert , et al. September 17, 2	2013-09-17
Post-placement cell shifting Grant 8,495,534 - Alpert , et al. July 23, 2	2013-07-23
Consideration of local routing and pin access during VLSI global routing Grant 8,418,113 - Alpert , et al. April 9, 2	2013-04-09
Accuracy pin-slew mode for gate delay calculation Grant 8,418,108 - Alpert , et al. April 9, 2	2013-04-09
Design Routability Using Multiplexer Structures App 20130086537 - Alpert; Charles J. ; et al.	2013-04-04
Evaluating Routing Congestion Based On Average Global Edge Congestion Histograms App 20130086545 - Alpert; Charles J. ; et al.	2013-04-04
Consideration Of Local Routing And Pin Access During Vlsi Global Routing App 20130086544 - Alpert; Charles J. ; et al.	2013-04-04
Resolving global coupling timing and slew violations for buffer-dominated designs Grant 8,365,120 - Alpert , et al. January 29, 2	2013-01-29
Detailed routability by cell placement Grant 8,347,257 - Alpert , et al. January 1, 2	2013-01-01
Incremental timing optimization and placement Grant 8,347,249 - Alpert , et al. January 1, 2	2013-01-01
Accuracy Pin-slew Mode For Gate Delay Calculation App 20120324409 - Alpert; Charles J. ; et al.	2012-12-20
Placement of Structured Nets App 20120266124 - Alpert; Charles J. ; et al.	2012-10-18
Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs App 20120144358 - Alpert; Charles J. ; et al.	2012-06-07
Clock Optimization with Local Clock Buffer Control Optimization App 20120124539 - Alpert; Charles J. ; et al.	2012-05-17
Electronic Design Automation Object Placement With Partially Region-constrained Objects App 20120054708 - Alpert; Charles J. ; et al.	2012-03-01
System and computer program product for diffusion based cell placement migration Grant 8,112,732 - Alpert , et al. February 7, 2	2012-02-07
Method and system for point-to-point fast delay estimation for VLSI circuits Grant 8,108,818 - Sze , et al. January 31, 2	2012-01-31
Method for diffusion based cell placement migration Grant 8,091,059 - Alpert , et al. January 3, 2	2012-01-03
Detailed Routability By Cell Placement App 20110302545 - Alpert; Charles J. ; et al.	2011-12-08
Post-placement Cell Shifting App 20110302544 - Alpert; Charles J. ; et al.	2011-12-08
Techniques for parallel buffer insertion Grant 8,037,438 - Li , et al. October 11, 2	2011-10-11
Optimal timing-driven cloning under linear delay model Grant 8,015,532 - Alpert , et al. September 6, 2	2011-09-06
Clock power minimization with regular physical placement of clock repeater components Grant 8,010,926 - Alpert , et al. August 30, 2	2011-08-30
Legalization of VLSI circuit placement with blockages using hierarchical row slicing Grant 7,934,188 - Alpert , et al. April 26, 2	2011-04-26
Concurrent buffering and layer assignment in integrated circuit layout Grant 7,895,557 - Alpert , et al. February 22, 2	2011-02-22
Slew constrained minimum cost buffering Grant 7,890,905 - Alpert , et al. February 15, 2	2011-02-15
Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors Grant 7,882,475 - Alpert , et al. February 1, 2	2011-02-01
Incremental Timing Optimization And Placement App 20100257498 - Alpert; Charles J. ; et al.	2010-10-07
Techniques For Fast Area-efficient Incremental Physical Synthesis App 20100257499 - Alpert; Charles J. ; et al.	2010-10-07
Techniques For Parallel Buffer Insertion App 20100223586 - Li; Zhuo ; et al.	2010-09-02
Method And System For Point-to-point Fast Delay Estimation For Vlsi Circuits App 20100199243 - Sze; Chin Ngai ; et al.	2010-08-05
Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model Grant 7,761,832 - Alpert , et al. July 20, 2	2010-07-20
Incremental timing-driven, physical-synthesis using discrete optimization Grant 7,707,530 - Alpert , et al. April 27, 2	2010-04-27
Clock aware placement Grant 7,624,366 - Alpert , et al. November 24, 2	2009-11-24
Legalization of VLSI circuit placement with blockages using hierarchical row slicing App 20090271752 - Alpert; Charles J. ; et al.	2009-10-29
Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout App 20090259980 - ALPERT; Charles J. ; et al.	2009-10-15
Clock Power Minimization With Regular Physical Placement Of Clock Repeater Components App 20090193376 - Alpert; Charles J. ; et al.	2009-07-30
Latch placement for high performance and low power circuits Grant 7,549,137 - Alpert , et al. June 16, 2	2009-06-16
Method for Incremental, Timing-Driven, Physical-Synthesis Using Discrete Optimization App 20090132981 - ALPERT; CHARLES J. ; et al.	2009-05-21
Method For Incremental, Timing-driven, Physical-synthesis Optimization Under A Linear Delay Model App 20090132970 - ALPERT; CHARLES J. ; et al.	2009-05-21
Methods for Optimal Timing-Driven Cloning Under Linear Delay Model App 20090125859 - Alpert; Charles J. ; et al.	2009-05-14
Method For Incremental, Timing-driven, Physical-synthesis Optimization App 20090089721 - Alpert; Charles J. ; et al.	2009-04-02
Buffer Insertion To Reduce Wirelength In Vlsi Circuits App 20090064080 - Alpert; Charles J. ; et al.	2009-03-05
Buffer insertion to reduce wirelength in VLSI circuits Grant 7,484,199 - Alpert , et al. January 27, 2	2009-01-27
Buffer Insertion To Reduce Wirelength In Vlsi Circuits App 20090013299 - Alpert; Charles J. ; et al.	2009-01-08
Constrained detailed placement Grant 7,467,369 - Alpert , et al. December 16, 2	2008-12-16
Slew Constrained Minimum Cost Buffering App 20080295051 - Alpert; Charles J. ; et al.	2008-11-27
Method and Apparatus for Congestion Based Physical Synthesis App 20080288905 - Alpert; Charles J. ; et al.	2008-11-20
Method To Reduce The Wirelength Of Analytical Placement Techniques By Modulation Of Spreading Forces Vectors App 20080282213 - Alpert; Charles J. ; et al.	2008-11-13
Slew constrained minimum cost buffering Grant 7,448,007 - Alpert , et al. November 4, 2	2008-11-04
Latch Placement for High Performance and Low Power Circuits App 20080148203 - Alpert; Charles J. ; et al.	2008-06-19
Constrained Detailed Placement App 20080127017 - Alpert; Charles J. ; et al.	2008-05-29
Clock Aware Placement App 20080127018 - Alpert; Charles J. ; et al.	2008-05-29
Method To Reduce The Wirelength Of Analytical Placement Techniques By Modulation Of Spreading Forces Vectors App 20080066037 - Alpert; Charles J. ; et al.	2008-03-13
Slew Constrained Minimum Cost Buffering App 20080016479 - Alpert; Charles J. ; et al.	2008-01-17
System and Method of Eliminating Electrical Violations App 20070283301 - Karandikar; Arvind K. ; et al.	2007-12-06
Buffer Insertion to Reduce Wirelength in VLSI Circuits App 20070271543 - Alpert; Charles J. ; et al.	2007-11-22
Analytical constraint generation for cut-based global placement Grant 6,671,867 - Alpert , et al. December 30, 2	2003-12-30
Analytical constraint generation for cut-based global placement App 20030196183 - Alpert, Charles J. ; et al.	2003-10-16