Alfke; Peter H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Alfke; Peter H..The latest application filed is for "direct digital synthesis with reduced jitter".

Company Profile

0.35.0

Alfke; Peter H. - Los Altos Hills CA
Alfke; Peter H. - Los Altos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Direct digital synthesis with reduced jitter Grant 8,352,526 - Alfke January 8, 2	2013-01-08
Circuit for measuring a time interval using a high-speed serial receiver Grant 8,265,902 - Brady , et al. September 11, 2	2012-09-11
Glitch-suppressor circuits and methods Grant 7,839,181 - Alfke November 23, 2	2010-11-23
Tapered signal lines Grant 7,759,801 - Lesea , et al. July 20, 2	2010-07-20
Reducing noise on a supply voltage in an integrated circuit Grant 7,755,381 - Alfke , et al. July 13, 2	2010-07-13
Glitch-suppressor circuits and methods Grant 7,667,500 - Alfke February 23, 2	2010-02-23
Circuit for and method of testing a memory device Grant 7,574,635 - Alfke August 11, 2	2009-08-11
Circuits and methods of concatenating FIFOs Grant 7,535,789 - Fischaber , et al. May 19, 2	2009-05-19
Tapered signal lines Grant 7,291,923 - Lesea , et al. November 6, 2	2007-11-06
Direct digital synthesis with low jitter Grant 7,268,594 - Alfke September 11, 2	2007-09-11
First-in, first-out memory system with reduced cycle latency Grant 7,254,677 - Lowe , et al. August 7, 2	2007-08-07
Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value Grant 7,227,387 - Alfke June 5, 2	2007-06-05
First-in, first-out buffer system in an integrated circuit Grant 7,161,849 - Lowe , et al. January 9, 2	2007-01-09
Large crossbar switch implemented in FPGA Grant 7,057,413 - Young , et al. June 6, 2	2006-06-06
Circuits and methods for analyzing timing characteristics of sequential logic elements Grant 7,020,862 - Alfke , et al. March 28, 2	2006-03-28
Almost full, almost empty memory system Grant 6,956,776 - Lowe , et al. October 18, 2	2005-10-18
Method and system for gray-coding counting Grant 6,937,172 - Lowe , et al. August 30, 2	2005-08-30
First-in, first-out buffer system in an integrated circuit Grant 6,934,198 - Lowe , et al. August 23, 2	2005-08-23
Controller arrangement for partial reconfiguration of a programmable logic device Grant 6,810,514 - Alfke , et al. October 26, 2	2004-10-26
Large crossbar switch implemented in FPGA Grant 6,759,869 - Young , et al. July 6, 2	2004-07-06
Circuits and methods for analyzing timing characteristics of sequential logic elements Grant 6,734,703 - Alfke , et al. May 11, 2	2004-05-11
Programmable logic device with partial battery backup Grant 6,441,641 - Pang , et al. August 27, 2	2002-08-27
FIFO memory system and method with improved determination of full and empty conditions and amount of data stored Grant 6,434,642 - Camilleri , et al. August 13, 2	2002-08-13
FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals Grant 6,389,490 - Camilleri , et al. May 14, 2	2002-05-14
FPGA control structure for self-reconfiguration Grant 6,260,139 - Alfke July 10, 2	2001-07-10
Clock-gating circuit for reducing power consumption Grant 6,204,695 - Alfke , et al. March 20, 2	2001-03-20
User-controlled delay circuit for a programmable logic device Grant 6,150,863 - Conn , et al. November 21, 2	2000-11-21
Oscillator for measuring on-chip delays Grant 6,134,191 - Alfke October 17, 2	2000-10-17
System for preventing radiation failures in programmable logic devices Grant 6,104,211 - Alfke August 15, 2	2000-08-15
Input signal interface with independently controllable pull-up and pull-down circuitry Grant 5,969,543 - Erickson , et al. October 19, 1	1999-10-19
Fifo memory system and method for controlling Grant 5,898,893 - Alfke April 27, 1	1999-04-27
Input signal interface with independently controllable pull-up and pull-down circuitry Grant 5,600,271 - Erickson , et al. February 4, 1	1997-02-04
Zero-crossing interpolator to reduce isochronous distortion in a digital FSK modem Grant 4,412,339 - Alfke , et al. October 25, 1	1983-10-25
Programmable counter Grant 4,084,082 - Alfke April 11, 1	1978-04-11
Phase-locked loop frequency synthesizer Grant 4,023,116 - Alfke , et al. May 10, 1	1977-05-10

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