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Dynamic Link Width Modulation
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Adjustment Of Execution Of Tasks
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Dynamic link width adjustment
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Dynamic link width modulation
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Exposing Protected Memory Addresses
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Controlling Power Consumption in Processor-Based Systems and Components Thereof
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Method and apparatus for optimizing power and latency on a link
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Method And Apparatus For Optimizing Power And Latency On A Link
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Method and system to improve the operations of a registered memory module
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Dynamic Link Width Adjustment
App 20140019654 - Trivedi; Malay ; et al. | 2014-01-16 |
Dynamic Link Width Modulation
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Method And System To Improve The Operations Of A Registered Memory Module
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Memory power management via dynamic memory operation states
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Systems, methods and apparatuses for clock enable (CKE) coordination
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Method and system to improve the operations of a registered memory module
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Mechanism for adjacent-symbol error correction and detection
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Memory Power Management Via Dynamic Memory Operation States
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Fully buffered DIMM read data substitution for write acknowledgement
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Systems, methods and apparatuses for rank coordination
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Resource power controller to return a resource to an up state based on an estimate of a size of a gap in data traffic
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Method And System To Improve The Operations Of A Registered Memory Module
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System and method for memory phase shedding
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Enabling An Integrated Memory Controller To Transparently Work With Defective Memory Devices
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Mitigating silent data corruption in a buffered memory module architecture
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Silent data corruption mitigation using error correction code with embedded signaling fault detection
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Optimizing Performance And Power Consumption During Memory Power Down State
App 20090249097 - Lam; Son H. ; et al. | 2009-10-01 |
Memory replay mechanism
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Coupled Low Power State Entry And Exit For Links And Memory
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Systems, Methods And Apparatuses For Rank Coordination
App 20090171875 - Alexander; James W. ; et al. | 2009-07-02 |
System And Method For Memory Phase Shedding
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Systems, Methods And Apparatuses For Clock Enable (cke) Coordination
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Hardware Proactive Implementation For Active Mode Power Control Of Platform Resources
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Mechanism for Adjacent-Symbol Error Correction and Detection
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Synchronized memory channels with unidirectional links
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Mechanism for adjacent-symbol error correction and detection
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Fully Buffered Dimm Read Data Substitution For Write Acknowledgement
App 20080320249 - Alexander; James W. ; et al. | 2008-12-25 |
Fully buffered DIMM read data substitution for write acknowledgement
Grant 7,444,479 - Alexander , et al. October 28, 2 | 2008-10-28 |
Resource power controller
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Chipset determinism for improved validation
App 20080005378 - Alexander; James W. ; et al. | 2008-01-03 |
Memory replay mechanism
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Synchronized memory channels with unidirectional links
App 20070156993 - Alexander; James W. ; et al. | 2007-07-05 |
Fully buffered DIMM read data substitution for write acknowledgement
App 20070150672 - Alexander; James W. ; et al. | 2007-06-28 |
Silent data corruption mitigation using error correction code with embedded signaling fault detection
App 20070089035 - Alexander; James W. ; et al. | 2007-04-19 |
Memory system anti-aliasing scheme
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Memory channel utilizing permuting status patterns
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Mitigating silent data corruption in a buffered memory module architecture
App 20070011562 - Alexander; James W. ; et al. | 2007-01-11 |
Mechanism for adjacent-symbol error correction and detection
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Memory channel utilizing permuting status patterns
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Method and apparatus for testing a logic device
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Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints
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