loadpatents
name:-0.021672964096069
name:-0.01726508140564
name:-0.016593933105469
Alexander; Gregory William Patent Filings

Alexander; Gregory William

Patent Applications and Registrations

Patent applications and USPTO patent grants for Alexander; Gregory William.The latest application filed is for "post completion execution in an out-of-order processor design".

Company Profile
16.15.16
  • Alexander; Gregory William - Pflugerville TX
  • Alexander; Gregory William - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Instruction scheduling during execution in a processor
Grant 11,256,511 - Lichtenau , et al. February 22, 2
2022-02-22
Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data
Grant 11,205,005 - Pardini , et al. December 21, 2
2021-12-21
Post completion execution in an out-of-order processor design
Grant 11,182,168 - Francois , et al. November 23, 2
2021-11-23
Write power optimization for hardware employing pipe-based duplicate register files
Grant 11,144,367 - Branciforte , et al. October 12, 2
2021-10-12
Store hit multiple load side register for preventing a subsequent store memory violation
Grant 11,144,321 - Fried , et al. October 12, 2
2021-10-12
Store instruction to store instruction dependency
Grant 11,113,055 - Malley , et al. September 7, 2
2021-09-07
Adjusting thread balancing in response to disruptive complex instruction
Grant 11,068,303 - Francois , et al. July 20, 2
2021-07-20
Post Completion Execution In An Out-of-order Processor Design
App 20210109758 - Francois; Avery ;   et al.
2021-04-15
Offset-based mechanism for storage in global completion tables
Grant 10,977,041 - Francois , et al. April 13, 2
2021-04-13
Accounting for multiple pipeline depths in processor instrumentation
Grant 10,963,259 - Francois , et al. March 30, 2
2021-03-30
Identifying Microarchitectural Security Vulnerabilities Using Simulation Comparison With Modified Secret Data
App 20210089659 - Pardini; Matthew Michael Garcia ;   et al.
2021-03-25
Post completion execution in an out-of-order processor design
Grant 10,956,168 - Francois , et al. March 23, 2
2021-03-23
Making precise operand-store-compare predictions to avoid false dependencies
Grant 10,929,142 - Alexander , et al. February 23, 2
2021-02-23
Accounting For Multiple Pipeline Depths In Processor Instrumentation
App 20200387378 - Francois; Avery ;   et al.
2020-12-10
Instruction Scheduling During Execution In A Processor
App 20200371810 - Lichtenau; Cedric ;   et al.
2020-11-26
Imprecise register dependency tracking
Grant 10,802,830 - Hsieh , et al. October 13, 2
2020-10-13
Store Instruction To Store Instruction Dependency
App 20200301706 - Malley; Edward ;   et al.
2020-09-24
Making Precise Operand-store-compare Predictions To Avoid False Dependencies
App 20200301710 - Alexander; Gregory William ;   et al.
2020-09-24
Post Completion Execution In An Out-of-order Processor Design
App 20200285482 - Francois; Avery ;   et al.
2020-09-10
Imprecise Register Dependency Tracking
App 20200285478 - Hsieh; Jonathan ;   et al.
2020-09-10
Offset-based Mechanism For Storage In Global Completion Tables
App 20200272468 - FRANCOIS; AVERY ;   et al.
2020-08-27
Adjusting Thread Balancing In Response To Disruptive Complex Instruction
App 20200264920 - Francois; Avery ;   et al.
2020-08-20
Store Hit Multiple Load Side Register For Operand Store Compare
App 20200264885 - Fried; Yair ;   et al.
2020-08-20
Write Power Optimization For Hardware Employing Pipe-based Duplicate Register Files
App 20200257572 - A1
2020-08-13
Register Deallocation In A Processing System
App 20200159535 - Bonanno; James ;   et al.
2020-05-21
Enhanced STCX design to improve subsequent load efficiency
Grant 7,254,678 - Alexander , et al. August 7, 2
2007-08-07
Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment
Grant 7,120,784 - Alexander , et al. October 10, 2
2006-10-10
Enhanced STCX design to improve subsequent load efficiency
App 20060212653 - Alexander; Gregory William ;   et al.
2006-09-21
Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions
Grant 7,039,768 - Alexander , et al. May 2, 2
2006-05-02
Cache predictor for simultaneous multi-threaded processor system supporting multiple translations
App 20040215882 - Alexander, Gregory William ;   et al.
2004-10-28
Split branch history tables and count cache for simultaneous multithreading
App 20040215720 - Alexander, Gregory William ;   et al.
2004-10-28

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